1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * egnite GmbH <info@egnite.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Configuation settings for Ethernut 5 with AT91SAM9XE. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CONFIG_H 11*4882a593Smuzhiyun #define __CONFIG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/hardware.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* The first stage boot loader expects u-boot running at this address. */ 16*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* The first stage boot loader takes care of low level initialization. */ 19*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Set our official architecture number. */ 22*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* CPU information */ 25*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* ARM asynchronous clock */ 28*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 29*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32kB internal SRAM */ 32*4882a593Smuzhiyun #define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ 33*4882a593Smuzhiyun #define CONFIG_SRAM_SIZE (32 << 10) 34*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ 35*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 128MB SDRAM in 1 bank */ 38*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 39*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x20000000 40*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (128 << 20) 41*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE 42*4882a593Smuzhiyun #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 43*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) 44*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 45*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ 46*4882a593Smuzhiyun - CONFIG_SYS_MALLOC_LEN) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 512kB on-chip NOR flash */ 49*4882a593Smuzhiyun # define CONFIG_SYS_MAX_FLASH_BANKS 1 50*4882a593Smuzhiyun # define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ 51*4882a593Smuzhiyun # define CONFIG_AT91_EFLASH 52*4882a593Smuzhiyun # define CONFIG_SYS_MAX_FLASH_SECT 32 53*4882a593Smuzhiyun # define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ 54*4882a593Smuzhiyun # define CONFIG_EFLASH_PROTSECTORS 1 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 58*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x3DE000 59*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (132 << 10) 60*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 61*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ 15000000 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifndef MINIMAL_LOADER 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* NAND flash */ 67*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 68*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 69*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x40000000 70*4882a593Smuzhiyun #define CONFIG_SYS_NAND_DBW_8 71*4882a593Smuzhiyun /* our ALE is AD21 */ 72*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 73*4882a593Smuzhiyun /* our CLE is AD22 */ 74*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 75*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* JFFS2 */ 79*4882a593Smuzhiyun #ifdef CONFIG_CMD_JFFS2 80*4882a593Smuzhiyun #define CONFIG_JFFS2_CMDLINE 81*4882a593Smuzhiyun #define CONFIG_JFFS2_NAND 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Ethernet */ 85*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 20 86*4882a593Smuzhiyun #define CONFIG_MACB 87*4882a593Smuzhiyun #define CONFIG_RMII 88*4882a593Smuzhiyun #define CONFIG_PHY_ID 0 89*4882a593Smuzhiyun #define CONFIG_MACB_SEARCH_PHY 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* MMC */ 92*4882a593Smuzhiyun #ifdef CONFIG_CMD_MMC 93*4882a593Smuzhiyun #define CONFIG_GENERIC_ATMEL_MCI 94*4882a593Smuzhiyun #define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* USB */ 98*4882a593Smuzhiyun #ifdef CONFIG_CMD_USB 99*4882a593Smuzhiyun #define CONFIG_USB_ATMEL 100*4882a593Smuzhiyun #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 101*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 102*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_CPU_INIT 103*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 104*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" 105*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 106*4882a593Smuzhiyun #endif 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* RTC */ 109*4882a593Smuzhiyun #if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) 110*4882a593Smuzhiyun #define CONFIG_RTC_PCF8563 111*4882a593Smuzhiyun #define CONFIG_SYS_I2C_RTC_ADDR 0x51 112*4882a593Smuzhiyun #endif 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* I2C */ 115*4882a593Smuzhiyun #define CONFIG_SYS_MAX_I2C_BUS 1 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define CONFIG_SYS_I2C 118*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 119*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SOFT_SPEED 100000 120*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SOFT_SLAVE 0 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define I2C_SOFT_DECLARATIONS 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define GPIO_I2C_SCL AT91_PIO_PORTA, 24 125*4882a593Smuzhiyun #define GPIO_I2C_SDA AT91_PIO_PORTA, 23 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define I2C_INIT { \ 128*4882a593Smuzhiyun at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ 129*4882a593Smuzhiyun at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 130*4882a593Smuzhiyun at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ 131*4882a593Smuzhiyun at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ 132*4882a593Smuzhiyun at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 133*4882a593Smuzhiyun } 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) 136*4882a593Smuzhiyun #define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) 137*4882a593Smuzhiyun #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 138*4882a593Smuzhiyun #define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) 139*4882a593Smuzhiyun #define I2C_DELAY udelay(100) 140*4882a593Smuzhiyun #define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* DHCP/BOOTP options */ 143*4882a593Smuzhiyun #ifdef CONFIG_CMD_DHCP 144*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 145*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 146*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 147*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 148*4882a593Smuzhiyun #define CONFIG_SYS_AUTOLOAD "n" 149*4882a593Smuzhiyun #endif 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* File systems */ 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* Boot command */ 154*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 155*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 156*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 157*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ 158*4882a593Smuzhiyun "sf read 0x22000000 0xc6000 0x294000; " \ 159*4882a593Smuzhiyun "bootm 0x22000000" 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* Misc. u-boot settings */ 162*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 163*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #endif 166