1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the ESPT-GIGA board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp. 5*4882a593Smuzhiyun * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ESPT_H 11*4882a593Smuzhiyun #define __ESPT_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_CPU_SH7763 1 14*4882a593Smuzhiyun #define CONFIG_ESPT 1 15*4882a593Smuzhiyun #define __LITTLE_ENDIAN 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 20*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* SCIF */ 23*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 26*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 27*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 28*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate 29*4882a593Smuzhiyun settings for this board */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SDRAM */ 32*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 33*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 34*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 35*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Flash(NOR) S29JL064H */ 38*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (0xA0000000) 39*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 40*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS (1) 41*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT (150) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* U-Boot setting */ 44*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 45*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 46*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 47*4882a593Smuzhiyun /* Size of DRAM reserved for malloc() use */ 48*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 49*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 52*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 53*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 54*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 55*4882a593Smuzhiyun /* Timeout for Flash erase operations (in ms) */ 56*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 57*4882a593Smuzhiyun /* Timeout for Flash write operations (in ms) */ 58*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 59*4882a593Smuzhiyun /* Timeout for Flash set sector lock bit operations (in ms) */ 60*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 61*4882a593Smuzhiyun /* Timeout for Flash clear lock bit operations (in ms) */ 62*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 63*4882a593Smuzhiyun /* Use hardware flash sectors protection instead of U-Boot software protection */ 64*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_PROTECTION 65*4882a593Smuzhiyun #undef CONFIG_SYS_DIRECT_FLASH_TFTP 66*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 67*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 68*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) 69*4882a593Smuzhiyun /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 70*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 71*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 72*4882a593Smuzhiyun #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Clock */ 75*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 66666666 76*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 77*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 78*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Ether */ 81*4882a593Smuzhiyun #define CONFIG_SH_ETHER 1 82*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT (1) 83*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR (0x00) 84*4882a593Smuzhiyun #define CONFIG_BITBANGMII 85*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 86*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* __SH7763RDP_H */ 89