1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Renesas Solutions ECOVEC board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2009 - 2011 Renesas Solutions Corp. 5*4882a593Smuzhiyun * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> 6*4882a593Smuzhiyun * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ECOVEC_H 12*4882a593Smuzhiyun #define __ECOVEC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Address Interface BusWidth 16*4882a593Smuzhiyun *----------------------------------------- 17*4882a593Smuzhiyun * 0x0000_0000 U-Boot 16bit 18*4882a593Smuzhiyun * 0x0004_0000 Linux romImage 16bit 19*4882a593Smuzhiyun * 0x0014_0000 MTD for Linux 16bit 20*4882a593Smuzhiyun * 0x0400_0000 Internal I/O 16/32bit 21*4882a593Smuzhiyun * 0x0800_0000 DRAM 32bit 22*4882a593Smuzhiyun * 0x1800_0000 MFI 16bit 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CONFIG_CPU_SH7724 1 26*4882a593Smuzhiyun #define CONFIG_ECOVEC 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000 29*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 32*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* I2C */ 35*4882a593Smuzhiyun #define CONFIG_SYS_I2C 36*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH 37*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x7F 38*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 39*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 40*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED0 100000 41*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 42*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED1 100000 43*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_HIGH 4 44*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_LOW 5 45*4882a593Smuzhiyun #define CONFIG_SH_I2C_CLOCK 41666666 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Ether */ 48*4882a593Smuzhiyun #define CONFIG_SH_ETHER 1 49*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT (0) 50*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR (0x1f) 51*4882a593Smuzhiyun #define CONFIG_PHY_SMSC 1 52*4882a593Smuzhiyun #define CONFIG_BITBANGMII 53*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 54*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* USB / R8A66597 */ 57*4882a593Smuzhiyun #define CONFIG_USB_R8A66597_HCD 58*4882a593Smuzhiyun #define CONFIG_R8A66597_BASE_ADDR 0xA4D80000 59*4882a593Smuzhiyun #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ 60*4882a593Smuzhiyun #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ 61*4882a593Smuzhiyun #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ 62*4882a593Smuzhiyun #define CONFIG_SUPERH_ON_CHIP_R8A66597 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* undef to save memory */ 65*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 66*4882a593Smuzhiyun /* Monitor Command Prompt */ 67*4882a593Smuzhiyun /* Buffer size for Console output */ 68*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 69*4882a593Smuzhiyun /* List of legal baudrate settings for this board */ 70*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* SCIF */ 73*4882a593Smuzhiyun #define CONFIG_SCIF 1 74*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Suppress display of console information at boot */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* SDRAM */ 79*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (0x88000000) 80*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) 81*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 84*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024) 85*4882a593Smuzhiyun /* Enable alternate, more extensive, memory test */ 86*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 87*4882a593Smuzhiyun /* Scratch address used by the alternate memory test */ 88*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Enable temporary baudrate change while serial download */ 91*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* FLASH */ 94*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 1 95*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 96*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 97*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO 98*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (0xA0000000) 99*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 512 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 102*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 103*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Timeout for Flash erase operations (in ms) */ 106*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 107*4882a593Smuzhiyun /* Timeout for Flash write operations (in ms) */ 108*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 109*4882a593Smuzhiyun /* Timeout for Flash set sector lock bit operations (in ms) */ 110*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 111*4882a593Smuzhiyun /* Timeout for Flash clear lock bit operations (in ms) */ 112*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* 115*4882a593Smuzhiyun * Use hardware flash sectors protection instead 116*4882a593Smuzhiyun * of U-Boot software protection 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_PROTECTION 119*4882a593Smuzhiyun #undef CONFIG_SYS_DIRECT_FLASH_TFTP 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 122*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 123*4882a593Smuzhiyun /* Monitor size */ 124*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 125*4882a593Smuzhiyun /* Size of DRAM reserved for malloc() use */ 126*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 127*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* ENV setting */ 130*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 131*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 132*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 133*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 134*4882a593Smuzhiyun /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 135*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 136*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* Board Clock */ 139*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 41666666 140*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 141*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 142*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif /* __ECOVEC_H */ 145