1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CONFIG_SYNOLOGY_DS414_H 8*4882a593Smuzhiyun #define _CONFIG_SYNOLOGY_DS414_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * High Level Configuration Options (easy to change) 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO_LATE 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17*4882a593Smuzhiyun * for DDR ECC byte filling in the SPL before loading the main 18*4882a593Smuzhiyun * U-Boot into it. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00800000 21*4882a593Smuzhiyun #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Commands configuration 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* I2C */ 28*4882a593Smuzhiyun #define CONFIG_SYS_I2C 29*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MVTWSI 30*4882a593Smuzhiyun #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 31*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x0 32*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* SPI NOR flash default params, used by sf commands */ 35*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 1000000 36*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Environment in SPI NOR flash */ 39*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */ 40*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 41*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 44*4882a593Smuzhiyun #define CONFIG_PHY_ADDR { 0x1, 0x0 } 45*4882a593Smuzhiyun #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CONFIG_SYS_ALT_MEMTEST 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* PCIe support */ 50*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 51*4882a593Smuzhiyun #define CONFIG_PCI_MVEBU 52*4882a593Smuzhiyun #define CONFIG_PCI_SCAN_SHOW 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* USB/EHCI/XHCI configuration */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* FIXME: broken XHCI support 60*4882a593Smuzhiyun * Below defines should enable support for the two rear USB3 ports. Sadly, this 61*4882a593Smuzhiyun * does not work because: 62*4882a593Smuzhiyun * - xhci-pci seems to not support DM_USB, so with that enabled it is not 63*4882a593Smuzhiyun * found. 64*4882a593Smuzhiyun * - USB init fails, controller does not respond in time */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #if !defined(CONFIG_USB_XHCI_HCD) 67*4882a593Smuzhiyun #define CONFIG_EHCI_IS_TDI 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* why is this only defined in mv-common.h if CONFIG_DM is undefined? */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * mv-common.h should be defined after CMD configs since it used them 74*4882a593Smuzhiyun * to enable certain macros 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #include "mv-common.h" 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * Memory layout while starting into the bin_hdr via the 80*4882a593Smuzhiyun * BootROM: 81*4882a593Smuzhiyun * 82*4882a593Smuzhiyun * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 83*4882a593Smuzhiyun * 0x4000.4030 bin_hdr start address 84*4882a593Smuzhiyun * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 85*4882a593Smuzhiyun * 0x4007.fffc BootROM stack top 86*4882a593Smuzhiyun * 87*4882a593Smuzhiyun * The address space between 0x4007.fffc and 0x400f.fff is not locked in 88*4882a593Smuzhiyun * L2 cache thus cannot be used. 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* SPL */ 92*4882a593Smuzhiyun /* Defines for SPL */ 93*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 94*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40004030 95*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 98*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 101*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_SIMPLE 102*4882a593Smuzhiyun #endif 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 105*4882a593Smuzhiyun #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* SPL related SPI defines */ 108*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 109*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* DS414 bus width is 32bits */ 112*4882a593Smuzhiyun #define CONFIG_DDR_32BIT 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Use random ethernet address if not configured */ 115*4882a593Smuzhiyun #define CONFIG_LIB_RAND 116*4882a593Smuzhiyun #define CONFIG_NET_RANDOM_ETHADDR 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Default Environment */ 119*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm" 120*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x80000 121*4882a593Smuzhiyun #undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */ 122*4882a593Smuzhiyun #define CONFIG_PREBOOT "usb start; sf probe" 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #endif /* _CONFIG_SYNOLOGY_DS414_H */ 125