1 /* 2 * Embest/Timll DevKit3250 board configuration file 3 * 4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_DEVKIT3250_H__ 10 #define __CONFIG_DEVKIT3250_H__ 11 12 /* SoC and board defines */ 13 #include <linux/sizes.h> 14 #include <asm/arch/cpu.h> 15 16 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 17 18 #define CONFIG_SYS_ICACHE_OFF 19 #define CONFIG_SYS_DCACHE_OFF 20 #if !defined(CONFIG_SPL_BUILD) 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #endif 23 24 /* 25 * Memory configurations 26 */ 27 #define CONFIG_NR_DRAM_BANKS 1 28 #define CONFIG_SYS_MALLOC_LEN SZ_1M 29 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 30 #define CONFIG_SYS_SDRAM_SIZE SZ_64M 31 #define CONFIG_SYS_TEXT_BASE 0x83F00000 32 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 34 35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 36 37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ 38 - GENERATED_GBL_DATA_SIZE) 39 40 /* 41 * Serial Driver 42 */ 43 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ 44 45 /* 46 * DMA 47 */ 48 #if !defined(CONFIG_SPL_BUILD) 49 #define CONFIG_DMA_LPC32XX 50 #endif 51 52 /* 53 * I2C 54 */ 55 #define CONFIG_SYS_I2C 56 #define CONFIG_SYS_I2C_LPC32XX 57 #define CONFIG_SYS_I2C_SPEED 100000 58 59 /* 60 * GPIO 61 */ 62 #define CONFIG_LPC32XX_GPIO 63 64 /* 65 * SSP/SPI 66 */ 67 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 68 69 /* 70 * Ethernet 71 */ 72 #define CONFIG_RMII 73 #define CONFIG_PHY_SMSC 74 #define CONFIG_LPC32XX_ETH 75 #define CONFIG_PHY_ADDR 0x1F 76 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 77 78 /* 79 * NOR Flash 80 */ 81 #define CONFIG_SYS_MAX_FLASH_BANKS 1 82 #define CONFIG_SYS_MAX_FLASH_SECT 71 83 #define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE 84 #define CONFIG_SYS_FLASH_SIZE SZ_4M 85 #define CONFIG_SYS_FLASH_CFI 86 87 /* 88 * NAND controller 89 */ 90 #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE 91 #define CONFIG_SYS_MAX_NAND_DEVICE 1 92 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 93 94 /* 95 * NAND chip timings 96 */ 97 #define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 98 #define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 99 #define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 100 #define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 101 #define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 102 #define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 103 #define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 104 #define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 105 106 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 107 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE 108 #define CONFIG_SYS_NAND_USE_FLASH_BBT 109 110 /* 111 * USB 112 */ 113 #define CONFIG_USB_OHCI_LPC32XX 114 #define CONFIG_USB_ISP1301_I2C_ADDR 0x2d 115 116 /* 117 * U-Boot General Configurations 118 */ 119 #define CONFIG_SYS_LONGHELP 120 #define CONFIG_SYS_CBSIZE 1024 121 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 122 123 #define CONFIG_AUTO_COMPLETE 124 #define CONFIG_CMDLINE_EDITING 125 126 /* 127 * Pass open firmware flat tree 128 */ 129 130 /* 131 * Environment 132 */ 133 #define CONFIG_ENV_SIZE SZ_128K 134 #define CONFIG_ENV_OFFSET 0x000A0000 135 136 #define CONFIG_BOOTCOMMAND \ 137 "dhcp; " \ 138 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ 139 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ 140 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ 141 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ 142 "bootm ${loadaddr} - ${dtbaddr}" 143 144 #define CONFIG_EXTRA_ENV_SETTINGS \ 145 "autoload=no\0" \ 146 "ethaddr=00:01:90:00:C0:81\0" \ 147 "dtbaddr=0x81000000\0" \ 148 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ 149 "tftpdir=vladimir/oe/devkit3250\0" \ 150 "userargs=oops=panic\0" 151 152 /* 153 * U-Boot Commands 154 */ 155 156 /* 157 * Boot Linux 158 */ 159 #define CONFIG_CMDLINE_TAG 160 #define CONFIG_SETUP_MEMORY_TAGS 161 162 #define CONFIG_BOOTFILE "uImage" 163 #define CONFIG_LOADADDR 0x80008000 164 165 /* 166 * SPL specific defines 167 */ 168 /* SPL will be executed at offset 0 */ 169 #define CONFIG_SPL_TEXT_BASE 0x00000000 170 171 /* SPL will use SRAM as stack */ 172 #define CONFIG_SPL_STACK 0x0000FFF8 173 174 /* Use the framework and generic lib */ 175 #define CONFIG_SPL_FRAMEWORK 176 177 /* SPL will use serial */ 178 179 /* SPL loads an image from NAND */ 180 #define CONFIG_SPL_NAND_RAW_ONLY 181 #define CONFIG_SPL_NAND_DRIVERS 182 183 #define CONFIG_SPL_NAND_ECC 184 #define CONFIG_SPL_NAND_SOFTECC 185 186 #define CONFIG_SPL_MAX_SIZE 0x20000 187 #define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE 188 189 /* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 190 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 191 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 192 193 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 194 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 195 196 /* See common/spl/spl.c spl_set_header_raw_uboot() */ 197 #define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE 198 199 /* 200 * Include SoC specific configuration 201 */ 202 #include <asm/arch/config.h> 203 204 #endif /* __CONFIG_DEVKIT3250_H__*/ 205