1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CONFIG_DB_MV7846MP_GP_H 8*4882a593Smuzhiyun #define _CONFIG_DB_MV7846MP_GP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * High Level Configuration Options (easy to change) 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO_LATE 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 19*4882a593Smuzhiyun * for DDR ECC byte filling in the SPL before loading the main 20*4882a593Smuzhiyun * U-Boot into it. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00800000 23*4882a593Smuzhiyun #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* I2C */ 26*4882a593Smuzhiyun #define CONFIG_SYS_I2C 27*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MVTWSI 28*4882a593Smuzhiyun #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 29*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x0 30*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* USB/EHCI configuration */ 33*4882a593Smuzhiyun #define CONFIG_EHCI_IS_TDI 34*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* SPI NOR flash default params, used by sf commands */ 37*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 1000000 38*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Environment in SPI NOR flash */ 41*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 42*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 43*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 46*4882a593Smuzhiyun #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define CONFIG_SYS_ALT_MEMTEST 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* SATA support */ 51*4882a593Smuzhiyun #define CONFIG_SYS_SATA_MAX_DEVICE 2 52*4882a593Smuzhiyun #define CONFIG_SATA_MV 53*4882a593Smuzhiyun #define CONFIG_LIBATA 54*4882a593Smuzhiyun #define CONFIG_LBA48 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Additional FS support/configuration */ 57*4882a593Smuzhiyun #define CONFIG_SUPPORT_VFAT 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* PCIe support */ 60*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 61*4882a593Smuzhiyun #define CONFIG_PCI_MVEBU 62*4882a593Smuzhiyun #define CONFIG_PCI_SCAN_SHOW 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* NAND */ 66*4882a593Smuzhiyun #define CONFIG_SYS_NAND_USE_FLASH_BBT 67*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * mv-common.h should be defined after CMD configs since it used them 71*4882a593Smuzhiyun * to enable certain macros 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #include "mv-common.h" 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * Memory layout while starting into the bin_hdr via the 77*4882a593Smuzhiyun * BootROM: 78*4882a593Smuzhiyun * 79*4882a593Smuzhiyun * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 80*4882a593Smuzhiyun * 0x4000.4030 bin_hdr start address 81*4882a593Smuzhiyun * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 82*4882a593Smuzhiyun * 0x4007.fffc BootROM stack top 83*4882a593Smuzhiyun * 84*4882a593Smuzhiyun * The address space between 0x4007.fffc and 0x400f.fff is not locked in 85*4882a593Smuzhiyun * L2 cache thus cannot be used. 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* SPL */ 89*4882a593Smuzhiyun /* Defines for SPL */ 90*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 91*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40004030 92*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 95*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 98*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_SIMPLE 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 102*4882a593Smuzhiyun #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* SPL related SPI defines */ 105*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 106*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 107*4882a593Smuzhiyun #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 110*4882a593Smuzhiyun #define CONFIG_SPD_EEPROM 0x4e 111*4882a593Smuzhiyun #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif /* _CONFIG_DB_MV7846MP_GP_H */ 114