1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Common board functions for siemens AT91SAM9G45 based boards 3*4882a593Smuzhiyun * (C) Copyright 2013 Siemens AG 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Based on: 6*4882a593Smuzhiyun * U-Boot file: include/configs/at91sam9m10g45ek.h 7*4882a593Smuzhiyun * (C) Copyright 2007-2008 8*4882a593Smuzhiyun * Stelian Pop <stelian@popies.net> 9*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __CONFIG_H 15*4882a593Smuzhiyun #define __CONFIG_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/hardware.h> 18*4882a593Smuzhiyun #include <linux/sizes.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Warning: changing CONFIG_SYS_TEXT_BASE requires 22*4882a593Smuzhiyun * adapting the initial boot program. 23*4882a593Smuzhiyun * Since the linker has to swallow that define, we must use a pure 24*4882a593Smuzhiyun * hex number here! 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x72000000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* ARM asynchronous clock */ 32*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 33*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 37*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 38*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* general purpose I/O */ 41*4882a593Smuzhiyun #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 42*4882a593Smuzhiyun #define CONFIG_AT91_GPIO 43*4882a593Smuzhiyun #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* serial console */ 46*4882a593Smuzhiyun #define CONFIG_USART_BASE ATMEL_BASE_DBGU 47*4882a593Smuzhiyun #define CONFIG_USART_ID ATMEL_ID_SYS 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* LED */ 50*4882a593Smuzhiyun #define CONFIG_AT91_LED 51*4882a593Smuzhiyun #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ 52*4882a593Smuzhiyun #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * BOOTP options 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 59*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 60*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 61*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* SDRAM */ 64*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 65*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 66*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x08000000 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 69*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* NAND flash */ 72*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 73*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 74*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 75*4882a593Smuzhiyun #define CONFIG_SYS_NAND_DBW_8 76*4882a593Smuzhiyun /* our ALE is AD21 */ 77*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 78*4882a593Smuzhiyun /* our CLE is AD22 */ 79*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 80*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 81*4882a593Smuzhiyun #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Ethernet */ 85*4882a593Smuzhiyun #define CONFIG_MACB 86*4882a593Smuzhiyun #define CONFIG_RMII 87*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 20 88*4882a593Smuzhiyun #define CONFIG_AT91_WANTS_COMMON_PHY 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* DFU class support */ 91*4882a593Smuzhiyun #define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) 92*4882a593Smuzhiyun #define DFU_MANIFEST_POLL_TIMEOUT 25000 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* bootstrap + u-boot + env in nandflash */ 97*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x100000 98*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND 0x180000 99*4882a593Smuzhiyun #define CONFIG_ENV_SIZE SZ_128K 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 102*4882a593Smuzhiyun "nand read 0x70000000 0x200000 0x300000;" \ 103*4882a593Smuzhiyun "bootm 0x70000000" 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 106*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 107*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * Size of malloc() pool 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 113*4882a593Smuzhiyun SZ_4M, 0x1000) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* Defines for SPL */ 116*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 117*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x300000 118*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) 119*4882a593Smuzhiyun #define CONFIG_SPL_STACK (SZ_16K) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE 122*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define CONFIG_SPL_NAND_DRIVERS 125*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BASE 126*4882a593Smuzhiyun #define CONFIG_SPL_NAND_ECC 127*4882a593Smuzhiyun #define CONFIG_SPL_NAND_RAW_ONLY 128*4882a593Smuzhiyun #define CONFIG_SPL_NAND_SOFTECC 129*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 130*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 131*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 132*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 133*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K 136*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) 137*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 138*4882a593Smuzhiyun CONFIG_SYS_NAND_PAGE_SIZE) 139*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 140*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCSIZE 256 141*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCBYTES 3 142*4882a593Smuzhiyun #define CONFIG_SYS_NAND_OOBSIZE 64 143*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 144*4882a593Smuzhiyun 48, 49, 50, 51, 52, 53, 54, 55, \ 145*4882a593Smuzhiyun 56, 57, 58, 59, 60, 61, 62, 63, } 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define CONFIG_SPL_ATMEL_SIZE 148*4882a593Smuzhiyun #define CONFIG_SYS_MASTER_CLOCK 132096000 149*4882a593Smuzhiyun #define AT91_PLL_LOCK_TIMEOUT 1000000 150*4882a593Smuzhiyun #define CONFIG_SYS_AT91_PLLA 0x20c73f03 151*4882a593Smuzhiyun #define CONFIG_SYS_MCKR 0x1301 152*4882a593Smuzhiyun #define CONFIG_SYS_MCKR_CSS 0x1302 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #endif 155