xref: /OK3568_Linux_fs/u-boot/include/configs/cm_t3517.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2013 CompuLab, Ltd.
3*4882a593Smuzhiyun  * Author: Igor Grinberg <grinberg@compulab.co.il>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Configuration settings for the CompuLab CM-T3517 board
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef __CONFIG_H
11*4882a593Smuzhiyun #define __CONFIG_H
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun  * High Level Configuration Options
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun #define CONFIG_CM_T3517	/* working with CM-T3517 */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE	0x80008000
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun  * This is needed for the DMA stuff.
22*4882a593Smuzhiyun  * Although the default iss 64, we still define it
23*4882a593Smuzhiyun  * to be on the safe side once the default is changed.
24*4882a593Smuzhiyun  */
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include <asm/arch/cpu.h>		/* get chip and board defs */
29*4882a593Smuzhiyun #include <asm/arch/omap.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define CONFIG_MACH_TYPE                MACH_TYPE_CM_T3517
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* Clock Defines */
34*4882a593Smuzhiyun #define V_OSCK			26000000	/* Clock output from T2 */
35*4882a593Smuzhiyun #define V_SCLK			(V_OSCK >> 1)
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun  * The early kernel mapping on ARM currently only maps from the base of DRAM
41*4882a593Smuzhiyun  * to the end of the kernel image.  The kernel is loaded at DRAM base + 0x8000.
42*4882a593Smuzhiyun  * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
43*4882a593Smuzhiyun  * so that leaves DRAM base to DRAM base + 0x4000 available.
44*4882a593Smuzhiyun  */
45*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ	        0x4000
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
48*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS
49*4882a593Smuzhiyun #define CONFIG_INITRD_TAG
50*4882a593Smuzhiyun #define CONFIG_REVISION_TAG
51*4882a593Smuzhiyun #define CONFIG_SERIAL_TAG
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun  * Size of malloc() pool
55*4882a593Smuzhiyun  */
56*4882a593Smuzhiyun #define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
57*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun  * Hardware drivers
61*4882a593Smuzhiyun  */
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun  * NS16550 Configuration
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_SERIAL
67*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
68*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun  * select serial console configuration
72*4882a593Smuzhiyun  */
73*4882a593Smuzhiyun #define CONFIG_CONS_INDEX		3
74*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
75*4882a593Smuzhiyun #define CONFIG_SERIAL3			3	/* UART3 */
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */
78*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE
79*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
80*4882a593Smuzhiyun 					115200}
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /* USB */
83*4882a593Smuzhiyun #define CONFIG_USB_MUSB_AM35X
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #ifndef CONFIG_USB_MUSB_AM35X
86*4882a593Smuzhiyun #define CONFIG_USB_OMAP3
87*4882a593Smuzhiyun #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
88*4882a593Smuzhiyun #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
89*4882a593Smuzhiyun #else /* !CONFIG_USB_MUSB_AM35X */
90*4882a593Smuzhiyun #define CONFIG_USB_MUSB_PIO_ONLY
91*4882a593Smuzhiyun #endif /* CONFIG_USB_MUSB_AM35X */
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /* commands to include */
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define CONFIG_SYS_I2C
96*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SPEED	400000
97*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
98*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
99*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
100*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_BUS	0
101*4882a593Smuzhiyun #define CONFIG_I2C_MULTI_BUS
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun  * Board NAND Info.
105*4882a593Smuzhiyun  */
106*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
107*4882a593Smuzhiyun 							/* to access nand */
108*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
109*4882a593Smuzhiyun 							/* to access nand at */
110*4882a593Smuzhiyun 							/* CS0 */
111*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
112*4882a593Smuzhiyun 							/* devices */
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /* Environment information */
115*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \
116*4882a593Smuzhiyun 	"loadaddr=0x82000000\0" \
117*4882a593Smuzhiyun 	"baudrate=115200\0" \
118*4882a593Smuzhiyun 	"console=ttyO2,115200n8\0" \
119*4882a593Smuzhiyun 	"netretry=yes\0" \
120*4882a593Smuzhiyun 	"mpurate=auto\0" \
121*4882a593Smuzhiyun 	"vram=12M\0" \
122*4882a593Smuzhiyun 	"dvimode=1024x768MR-16@60\0" \
123*4882a593Smuzhiyun 	"defaultdisplay=dvi\0" \
124*4882a593Smuzhiyun 	"mmcdev=0\0" \
125*4882a593Smuzhiyun 	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
126*4882a593Smuzhiyun 	"mmcrootfstype=ext4\0" \
127*4882a593Smuzhiyun 	"nandroot=/dev/mtdblock4 rw\0" \
128*4882a593Smuzhiyun 	"nandrootfstype=ubifs\0" \
129*4882a593Smuzhiyun 	"mmcargs=setenv bootargs console=${console} " \
130*4882a593Smuzhiyun 		"mpurate=${mpurate} " \
131*4882a593Smuzhiyun 		"vram=${vram} " \
132*4882a593Smuzhiyun 		"omapfb.mode=dvi:${dvimode} " \
133*4882a593Smuzhiyun 		"omapdss.def_disp=${defaultdisplay} " \
134*4882a593Smuzhiyun 		"root=${mmcroot} " \
135*4882a593Smuzhiyun 		"rootfstype=${mmcrootfstype}\0" \
136*4882a593Smuzhiyun 	"nandargs=setenv bootargs console=${console} " \
137*4882a593Smuzhiyun 		"mpurate=${mpurate} " \
138*4882a593Smuzhiyun 		"vram=${vram} " \
139*4882a593Smuzhiyun 		"omapfb.mode=dvi:${dvimode} " \
140*4882a593Smuzhiyun 		"omapdss.def_disp=${defaultdisplay} " \
141*4882a593Smuzhiyun 		"root=${nandroot} " \
142*4882a593Smuzhiyun 		"rootfstype=${nandrootfstype}\0" \
143*4882a593Smuzhiyun 	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
144*4882a593Smuzhiyun 	"bootscript=echo Running bootscript from mmc ...; " \
145*4882a593Smuzhiyun 		"source ${loadaddr}\0" \
146*4882a593Smuzhiyun 	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
147*4882a593Smuzhiyun 	"mmcboot=echo Booting from mmc ...; " \
148*4882a593Smuzhiyun 		"run mmcargs; " \
149*4882a593Smuzhiyun 		"bootm ${loadaddr}\0" \
150*4882a593Smuzhiyun 	"nandboot=echo Booting from nand ...; " \
151*4882a593Smuzhiyun 		"run nandargs; " \
152*4882a593Smuzhiyun 		"nand read ${loadaddr} 2a0000 400000; " \
153*4882a593Smuzhiyun 		"bootm ${loadaddr}\0" \
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \
156*4882a593Smuzhiyun 	"mmc dev ${mmcdev}; if mmc rescan; then " \
157*4882a593Smuzhiyun 		"if run loadbootscript; then " \
158*4882a593Smuzhiyun 			"run bootscript; " \
159*4882a593Smuzhiyun 		"else " \
160*4882a593Smuzhiyun 			"if run loaduimage; then " \
161*4882a593Smuzhiyun 				"run mmcboot; " \
162*4882a593Smuzhiyun 			"else run nandboot; " \
163*4882a593Smuzhiyun 			"fi; " \
164*4882a593Smuzhiyun 		"fi; " \
165*4882a593Smuzhiyun 	"else run nandboot; fi"
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun /*
168*4882a593Smuzhiyun  * Miscellaneous configurable options
169*4882a593Smuzhiyun  */
170*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE
171*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING
172*4882a593Smuzhiyun #define CONFIG_TIMESTAMP
173*4882a593Smuzhiyun #define CONFIG_SYS_AUTOLOAD		"no"
174*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP		/* undef to save memory */
175*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
176*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS		32	/* max number of command args */
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /*
181*4882a593Smuzhiyun  * AM3517 has 12 GP timers, they can be driven by the system clock
182*4882a593Smuzhiyun  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
183*4882a593Smuzhiyun  * This rate is divided by a local divisor.
184*4882a593Smuzhiyun  */
185*4882a593Smuzhiyun #define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
186*4882a593Smuzhiyun #define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
187*4882a593Smuzhiyun #define CONFIG_SYS_HZ			1000
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /*-----------------------------------------------------------------------
190*4882a593Smuzhiyun  * Physical Memory Map
191*4882a593Smuzhiyun  */
192*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS	1	/* CM-T3517 DRAM is only on CS0 */
193*4882a593Smuzhiyun #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
194*4882a593Smuzhiyun #define CONFIG_SYS_CS0_SIZE		(256 << 20)
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun /*-----------------------------------------------------------------------
197*4882a593Smuzhiyun  * FLASH and environment organization
198*4882a593Smuzhiyun  */
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /* **** PISMO SUPPORT *** */
201*4882a593Smuzhiyun /* Monitor at start of flash */
202*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
203*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
206*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
207*4882a593Smuzhiyun #define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun #if defined(CONFIG_CMD_NET)
210*4882a593Smuzhiyun #define CONFIG_DRIVER_TI_EMAC
211*4882a593Smuzhiyun #define CONFIG_DRIVER_TI_EMAC_USE_RMII
212*4882a593Smuzhiyun #define CONFIG_MII
213*4882a593Smuzhiyun #define CONFIG_SMC911X
214*4882a593Smuzhiyun #define CONFIG_SMC911X_32_BIT
215*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE	(0x2C000000 + (16 << 20))
216*4882a593Smuzhiyun #define CONFIG_ARP_TIMEOUT		200UL
217*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT		5
218*4882a593Smuzhiyun #endif /* CONFIG_CMD_NET */
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun /* additions for new relocation code, must be added to all boards */
221*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
222*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
223*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE	0x800
224*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
225*4882a593Smuzhiyun 					 CONFIG_SYS_INIT_RAM_SIZE -	\
226*4882a593Smuzhiyun 					 GENERATED_GBL_DATA_SIZE)
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun /* Status LED */
229*4882a593Smuzhiyun #define GREEN_LED_GPIO			186 /* CM-T3517 Green LED is GPIO186 */
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun /* Display Configuration */
232*4882a593Smuzhiyun #define CONFIG_VIDEO_OMAP3
233*4882a593Smuzhiyun #define LCD_BPP		LCD_COLOR16
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun #define CONFIG_SPLASH_SCREEN
236*4882a593Smuzhiyun #define CONFIG_SPLASHIMAGE_GUARD
237*4882a593Smuzhiyun #define CONFIG_BMP_16BPP
238*4882a593Smuzhiyun #define CONFIG_SCF0403_LCD
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun /* EEPROM */
241*4882a593Smuzhiyun #define CONFIG_ENV_EEPROM_IS_ON_I2C
242*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
243*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
244*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
245*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_SIZE			256
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun #endif /* __CONFIG_H */
248