1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * bur_am335x_common.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * common parts used by B&R AM335x based boards 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - 7*4882a593Smuzhiyun * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __BUR_AM335X_COMMON_H__ 13*4882a593Smuzhiyun #define __BUR_AM335X_COMMON_H__ 14*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 15*4882a593Smuzhiyun #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Timer information */ 18*4882a593Smuzhiyun #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 19*4882a593Smuzhiyun #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 20*4882a593Smuzhiyun #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */ 21*4882a593Smuzhiyun #define CONFIG_POWER_TPS65217 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #include <asm/arch/omap.h> 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* NS16550 Configuration */ 26*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_SERIAL 27*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_REG_SIZE (-4) 28*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK 48000000 29*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Network defines */ 32*4882a593Smuzhiyun #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ 33*4882a593Smuzhiyun #define CONFIG_MII /* Required in net/eth.c */ 34*4882a593Smuzhiyun #define CONFIG_PHY_NATSEMI 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * SPL related defines. The Public RAM memory map the ROM defines the 38*4882a593Smuzhiyun * area between 0x402F0400 and 0x4030B800 as a download area and 39*4882a593Smuzhiyun * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also 40*4882a593Smuzhiyun * supports X-MODEM loading via UART, and we leverage this and then use 41*4882a593Smuzhiyun * Y-MODEM to load u-boot.img, when booted over UART. We must also include 42*4882a593Smuzhiyun * the scratch space that U-Boot uses in SRAM. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x402F0400 45*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 46*4882a593Smuzhiyun CONFIG_SPL_TEXT_BASE) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Since SPL did pll and ddr initialization for us, 50*4882a593Smuzhiyun * we don't need to do it twice. 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) 53*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 54*4882a593Smuzhiyun #endif /* !CONFIG_SPL_BUILD, ... */ 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * Our DDR memory always starts at 0x80000000 and U-Boot shall have 57*4882a593Smuzhiyun * relocated itself to higher in memory by the time this value is used. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x80000000 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 62*4882a593Smuzhiyun * DDR information. We say (for simplicity) that we have 1 bank, 63*4882a593Smuzhiyun * always, even when we have more. We always start at 0x80000000, 64*4882a593Smuzhiyun * and we place the initial stack pointer in our SRAM. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 67*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x80000000 68*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 69*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* I2C */ 72*4882a593Smuzhiyun #define CONFIG_SYS_I2C 73*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 74*4882a593Smuzhiyun #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* 77*4882a593Smuzhiyun * Our platforms make use of SPL to initalize the hardware (primarily 78*4882a593Smuzhiyun * memory) enough for full U-Boot to be loaded. We also support Falcon 79*4882a593Smuzhiyun * Mode so that the Linux kernel can be booted directly from SPL 80*4882a593Smuzhiyun * instead, if desired. We make use of the general SPL framework found 81*4882a593Smuzhiyun * under common/spl/. Given our generally common memory map, we set a 82*4882a593Smuzhiyun * number of related defaults and sizes here. 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * Place the image at the start of the ROM defined image space. 87*4882a593Smuzhiyun * We limit our size to the ROM-defined downloaded image area, and use the 88*4882a593Smuzhiyun * rest of the space for stack. We load U-Boot itself into memory at 89*4882a593Smuzhiyun * 0x80800000 for legacy reasons (to not conflict with older SPLs). We 90*4882a593Smuzhiyun * have our BSS be placed 1MiB after this, to allow for the default 91*4882a593Smuzhiyun * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. 92*4882a593Smuzhiyun * We have the SPL malloc pool at the end of the BSS area. 93*4882a593Smuzhiyun * 94*4882a593Smuzhiyun * ---------------------------------------------------------------------------- 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #undef CONFIG_SYS_TEXT_BASE 97*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x80800000 98*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 99*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 100*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 101*4882a593Smuzhiyun CONFIG_SPL_BSS_MAX_SIZE) 102*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* General parts of the framework, required. */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #endif /* ! __BUR_AM335X_COMMON_H__ */ 107