1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/blanche.h 3*4882a593Smuzhiyun * This file is blanche board configuration. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __BLANCHE_H 11*4882a593Smuzhiyun #define __BLANCHE_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #undef DEBUG 14*4882a593Smuzhiyun #define CONFIG_R8A7792 15*4882a593Smuzhiyun #define CONFIG_RMOBILE_BOARD_STRING "Blanche" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "rcar-gen2-common.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* STACK */ 20*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xE817FFFC 21*4882a593Smuzhiyun #define STACK_AREA_SIZE 0xC000 22*4882a593Smuzhiyun #define LOW_LEVEL_MERAM_STACK \ 23*4882a593Smuzhiyun (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* MEMORY */ 26*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_BASE 0x40000000 27*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 28*4882a593Smuzhiyun #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* SCIF */ 31*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (RCAR_GEN2_SDRAM_BASE) 34*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 37*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 38*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* FLASH */ 41*4882a593Smuzhiyun #if !defined(CONFIG_MTD_NOR_FLASH) 42*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x40000000 43*4882a593Smuzhiyun #define CONFIG_SPI 44*4882a593Smuzhiyun #define CONFIG_SH_QSPI_BASE 0xE6B10000 45*4882a593Smuzhiyun #else 46*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00000000 47*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 48*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 49*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 50*4882a593Smuzhiyun #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 51*4882a593Smuzhiyun #define CONFIG_FLASH_SHOW_PROGRESS 45 52*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x00000000 53*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ 54*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 1024 55*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 56*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } 57*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 3000 60*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT 3000 61*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_LOCK_TOUT 3000 62*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 63*4882a593Smuzhiyun #undef CONFIG_CMD_SF 64*4882a593Smuzhiyun #undef CONFIG_CMD_SPI 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* BLANCHE on board LANC: SMC89218 (ExCS0) */ 68*4882a593Smuzhiyun #define CONFIG_NET_MULTI 69*4882a593Smuzhiyun #define CONFIG_SMC911X 1 70*4882a593Smuzhiyun #define CONFIG_SMC911X_16_BIT 1 71*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE 0x18000000 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Board Clock */ 74*4882a593Smuzhiyun #define RMOBILE_XTAL_CLK 20000000u 75*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 76*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 77*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* ENV setting */ 80*4882a593Smuzhiyun #if !defined(CONFIG_MTD_NOR_FLASH) 81*4882a593Smuzhiyun #else 82*4882a593Smuzhiyun #undef CONFIG_ENV_ADDR 83*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (256 * 1024) 84*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 85*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 86*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 87*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) 88*4882a593Smuzhiyun #endif 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Module stop status bits */ 91*4882a593Smuzhiyun /* INTC-RT */ 92*4882a593Smuzhiyun #define CONFIG_SMSTP0_ENA 0x00400000 93*4882a593Smuzhiyun /* SDHI0 */ 94*4882a593Smuzhiyun #define CONFIG_SMSTP3_ENA 0x00004000 95*4882a593Smuzhiyun /* INTC-SYS, IRQC */ 96*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 97*4882a593Smuzhiyun /* SCIF0 */ 98*4882a593Smuzhiyun #define CONFIG_SMSTP7_ENA 0x00200000 99*4882a593Smuzhiyun /* QSPI */ 100*4882a593Smuzhiyun #define CONFIG_SMSTP9_ENA 0x00020000 101*4882a593Smuzhiyun /* SYS-DMAC0 */ 102*4882a593Smuzhiyun #define CONFIG_RMSTP2_ENA 0x00080000 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* SDHI */ 105*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 97500000 106*4882a593Smuzhiyun #define HAVE_BLOCK_DEVICE 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* __BLANCHE_H */ 109