1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CONFIG_AXS10X_H_ 8*4882a593Smuzhiyun #define _CONFIG_AXS10X_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/sizes.h> 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * CPU configuration 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 15*4882a593Smuzhiyun #define ARC_APB_PERIPHERAL_BASE 0xF0000000 16*4882a593Smuzhiyun #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) 17*4882a593Smuzhiyun #define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * Memory configuration 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 25*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 26*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE SZ_512M 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 29*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN SZ_2M 32*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN SZ_32M 33*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x82000000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * This board might be of different versions so handle it 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define CONFIG_BOARD_TYPES 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * NAND Flash configuration 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) 44*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * UART configuration 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define CONFIG_DW_SERIAL 50*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_SERIAL 51*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK 33333333 52*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_MEM32 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Ethernet PHY configuration 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define CONFIG_MII 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * USB 1.1 configuration 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 63*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 66*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * Environment settings 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun #define CONFIG_ENV_SIZE SZ_16K 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * Environment configuration 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define CONFIG_BOOTFILE "uImage" 77*4882a593Smuzhiyun #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 80*4882a593Smuzhiyun * Console configuration 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * Misc utility configuration 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* _CONFIG_AXS10X_H_ */ 90