1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Atmel Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Configuation settings for the AT91SAM9X5EK board. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __CONFIG_H__ 10*4882a593Smuzhiyun #define __CONFIG_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/hardware.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x26f00000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* ARM asynchronous clock */ 17*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 18*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_AT91SAM9X5EK 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 23*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 24*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 25*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* general purpose I/O */ 28*4882a593Smuzhiyun #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* LCD */ 31*4882a593Smuzhiyun #define LCD_BPP LCD_COLOR16 32*4882a593Smuzhiyun #define LCD_OUTPUT_BPP 24 33*4882a593Smuzhiyun #define CONFIG_LCD_LOGO 34*4882a593Smuzhiyun #define CONFIG_LCD_INFO 35*4882a593Smuzhiyun #define CONFIG_LCD_INFO_BELOW_LOGO 36*4882a593Smuzhiyun #define CONFIG_ATMEL_HLCD 37*4882a593Smuzhiyun #define CONFIG_ATMEL_LCD_RGB565 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * BOOTP options 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 44*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 45*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 46*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) 50*4882a593Smuzhiyun * NB: in this case, USB 1.1 devices won't be recognized. 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* SDRAM */ 54*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 55*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x20000000 56*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 59*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* DataFlash */ 62*4882a593Smuzhiyun #ifdef CONFIG_CMD_SF 63*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 30000000 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* NAND flash */ 67*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 68*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 69*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x40000000 70*4882a593Smuzhiyun #define CONFIG_SYS_NAND_DBW_8 1 71*4882a593Smuzhiyun /* our ALE is AD21 */ 72*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 73*4882a593Smuzhiyun /* our CLE is AD22 */ 74*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 75*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 76*4882a593Smuzhiyun #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* USB */ 80*4882a593Smuzhiyun #ifdef CONFIG_CMD_USB 81*4882a593Smuzhiyun #ifndef CONFIG_USB_EHCI_HCD 82*4882a593Smuzhiyun #define CONFIG_USB_ATMEL 83*4882a593Smuzhiyun #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 84*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 85*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_CPU_INIT 86*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 87*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" 88*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun #endif 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 95*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x26e00000 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #ifdef CONFIG_SYS_USE_NANDFLASH 98*4882a593Smuzhiyun /* bootstrap + u-boot + env + linux in nandflash */ 99*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x120000 100*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND 0x100000 101*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 102*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "nand read " \ 103*4882a593Smuzhiyun "0x22000000 0x200000 0x300000; " \ 104*4882a593Smuzhiyun "bootm 0x22000000" 105*4882a593Smuzhiyun #elif defined(CONFIG_SYS_USE_SPIFLASH) 106*4882a593Smuzhiyun /* bootstrap + u-boot + env + linux in spi flash */ 107*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x5000 108*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x3000 109*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x1000 110*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ 30000000 111*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 112*4882a593Smuzhiyun "sf read 0x22000000 0x100000 0x300000; " \ 113*4882a593Smuzhiyun "bootm 0x22000000" 114*4882a593Smuzhiyun #elif defined(CONFIG_SYS_USE_DATAFLASH) 115*4882a593Smuzhiyun /* bootstrap + u-boot + env + linux in data flash */ 116*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x4200 117*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x4200 118*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x210 119*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ 30000000 120*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "sf probe 0; " \ 121*4882a593Smuzhiyun "sf read 0x22000000 0x84000 0x294000; " \ 122*4882a593Smuzhiyun "bootm 0x22000000" 123*4882a593Smuzhiyun #else /* CONFIG_SYS_USE_MMC */ 124*4882a593Smuzhiyun /* bootstrap + u-boot + env + linux in mmc */ 125*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x4000 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 129*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 130*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* 133*4882a593Smuzhiyun * Size of malloc() pool 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* SPL */ 138*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 139*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x300000 140*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x6000 141*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x308000 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x20000000 144*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 145*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 146*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 << 10) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define CONFIG_SYS_MASTER_CLOCK 132096000 151*4882a593Smuzhiyun #define CONFIG_SYS_AT91_PLLA 0x20c73f03 152*4882a593Smuzhiyun #define CONFIG_SYS_MCKR 0x1301 153*4882a593Smuzhiyun #define CONFIG_SYS_MCKR_CSS 0x1302 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #ifdef CONFIG_SYS_USE_MMC 156*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 157*4882a593Smuzhiyun #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #elif CONFIG_SYS_USE_NANDFLASH 160*4882a593Smuzhiyun #define CONFIG_SPL_NAND_DRIVERS 161*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BASE 162*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 163*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 164*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 165*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 166*4882a593Smuzhiyun #define CONFIG_SYS_NAND_OOBSIZE 64 167*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 168*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #elif CONFIG_SYS_USE_SPIFLASH 171*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 172*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #endif 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #endif 177