1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * based on previous work by 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Ulf Samuelsson <ulf@atmel.com> 7*4882a593Smuzhiyun * Rick Bronson <rick@efn.org> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Configuration settings for the AT91RM9200EK board. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __AT91RM9200EK_CONFIG_H__ 15*4882a593Smuzhiyun #define __AT91RM9200EK_CONFIG_H__ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <linux/sizes.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * set some initial configurations depending on configure target 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0 23*4882a593Smuzhiyun * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel 24*4882a593Smuzhiyun * initialisation was done by some preloader 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #ifdef CONFIG_RAMBOOT 27*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 28*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x20100000 29*4882a593Smuzhiyun #else 30*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x10000000 31*4882a593Smuzhiyun #endif 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz 35*4882a593Smuzhiyun * AT91C_MAIN_CLOCK is the frequency of PLLA output 36*4882a593Smuzhiyun * AT91C_MASTER_CLOCK is the peripherial clock 37*4882a593Smuzhiyun * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely 38*4882a593Smuzhiyun * set in arch/arm/cpu/arm920t/at91/timer.c) 39*4882a593Smuzhiyun * CONFIG_SYS_HZ is the tick rate for timer tc0 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define AT91C_XTAL_CLOCK 18432000 42*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 43*4882a593Smuzhiyun #define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) 44*4882a593Smuzhiyun #define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) 45*4882a593Smuzhiyun #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* CPU configuration */ 48*4882a593Smuzhiyun #define CONFIG_AT91RM9200 49*4882a593Smuzhiyun #define CONFIG_AT91RM9200EK 50*4882a593Smuzhiyun #define CONFIG_CPUAT91 51*4882a593Smuzhiyun #define USE_920T_MMU 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #include <asm/hardware.h> /* needed for port definitions */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 56*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 57*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * Memory Configuration 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 63*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x20000000 64*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE SZ_32M 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 67*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END \ 68*4882a593Smuzhiyun (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* 71*4882a593Smuzhiyun * LowLevel Init 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun #ifndef CONFIG_SKIP_LOWLEVEL_INIT 74*4882a593Smuzhiyun #define CONFIG_SYS_USE_MAIN_OSCILLATOR 75*4882a593Smuzhiyun /* flash */ 76*4882a593Smuzhiyun #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 77*4882a593Smuzhiyun #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* clocks */ 80*4882a593Smuzhiyun #define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ 81*4882a593Smuzhiyun #define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ 82*4882a593Smuzhiyun /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ 83*4882a593Smuzhiyun #define CONFIG_SYS_MCKR_VAL 0x00000202 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* sdram */ 86*4882a593Smuzhiyun #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ 87*4882a593Smuzhiyun #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 88*4882a593Smuzhiyun #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 89*4882a593Smuzhiyun #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ 90*4882a593Smuzhiyun #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ 91*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ 92*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80) 93*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ 94*4882a593Smuzhiyun #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ 95*4882a593Smuzhiyun #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ 96*4882a593Smuzhiyun #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ 97*4882a593Smuzhiyun #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ 98*4882a593Smuzhiyun #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ 99*4882a593Smuzhiyun #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* 102*4882a593Smuzhiyun * Hardware drivers 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * Choose a USART for serial console 106*4882a593Smuzhiyun * CONFIG_DBGU is DBGU unit on J10 107*4882a593Smuzhiyun * CONFIG_USART1 is USART1 on J14 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun #define CONFIG_ATMEL_USART 110*4882a593Smuzhiyun #define CONFIG_USART_BASE ATMEL_BASE_DBGU 111*4882a593Smuzhiyun #define CONFIG_USART_ID 0/* ignored in arm */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Command line configuration. 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* 118*4882a593Smuzhiyun * Network Driver Setting 119*4882a593Smuzhiyun */ 120*4882a593Smuzhiyun #define CONFIG_DRIVER_AT91EMAC 121*4882a593Smuzhiyun #define CONFIG_SYS_RX_ETH_BUFFER 16 122*4882a593Smuzhiyun #define CONFIG_RMII 123*4882a593Smuzhiyun #define CONFIG_MII 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* 126*4882a593Smuzhiyun * NOR Flash 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 129*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 130*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x10000000 131*4882a593Smuzhiyun #define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE 132*4882a593Smuzhiyun #define PHYS_FLASH_SIZE SZ_8M 133*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 134*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 256 135*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_PROTECTION 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* 138*4882a593Smuzhiyun * USB Config 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun #define CONFIG_USB_ATMEL 1 141*4882a593Smuzhiyun #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 142*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 1 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 145*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE 146*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" 147*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* 150*4882a593Smuzhiyun * Environment Settings 151*4882a593Smuzhiyun */ 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* 154*4882a593Smuzhiyun * after u-boot.bin 155*4882a593Smuzhiyun */ 156*4882a593Smuzhiyun #define CONFIG_ENV_ADDR \ 157*4882a593Smuzhiyun (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 158*4882a593Smuzhiyun #define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */ 159*4882a593Smuzhiyun /* The following #defines are needed to get flash environment right */ 160*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 161*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN SZ_256K 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* 164*4882a593Smuzhiyun * Boot option 165*4882a593Smuzhiyun */ 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* default load address */ 168*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M 169*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * Shell Settings 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 175*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 176*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* 179*4882a593Smuzhiyun * Size of malloc() pool 180*4882a593Smuzhiyun */ 181*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ 182*4882a593Smuzhiyun SZ_4K) 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ 185*4882a593Smuzhiyun - GENERATED_GBL_DATA_SIZE) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #endif /* __AT91RM9200EK_CONFIG_H__ */ 188