1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration settings for the Sentec Cobra Board. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * configuration for ASTRO "Urmel" board. 11*4882a593Smuzhiyun * Originating from Cobra5272 configuration, messed up by 12*4882a593Smuzhiyun * Wolfgang Wegner <w.wegner@astro-kom.de> 13*4882a593Smuzhiyun * Please do not bother the original author with bug reports 14*4882a593Smuzhiyun * concerning this file. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef _CONFIG_ASTRO_MCF5373L_H 18*4882a593Smuzhiyun #define _CONFIG_ASTRO_MCF5373L_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <linux/stringify.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * set the card type to actually compile for; either of 24*4882a593Smuzhiyun * the possibilities listed below has to be used! 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define CONFIG_ASTRO_V532 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #if CONFIG_ASTRO_V532 29*4882a593Smuzhiyun #define ASTRO_ID 0xF8 30*4882a593Smuzhiyun #elif CONFIG_ASTRO_V512 31*4882a593Smuzhiyun #define ASTRO_ID 0xFA 32*4882a593Smuzhiyun #elif CONFIG_ASTRO_TWIN7S2 33*4882a593Smuzhiyun #define ASTRO_ID 0xF9 34*4882a593Smuzhiyun #elif CONFIG_ASTRO_V912 35*4882a593Smuzhiyun #define ASTRO_ID 0xFC 36*4882a593Smuzhiyun #elif CONFIG_ASTRO_COFDMDUOS2 37*4882a593Smuzhiyun #define ASTRO_ID 0xFB 38*4882a593Smuzhiyun #else 39*4882a593Smuzhiyun #error No card type defined! 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CONFIG_ASTRO5373L /* define board type */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Command line configuration */ 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * CONFIG_RAM defines if u-boot is loaded via BDM (or started from 47*4882a593Smuzhiyun * a different bootloader that has already performed RAM setup) or 48*4882a593Smuzhiyun * started directly from flash, which is the regular case for production 49*4882a593Smuzhiyun * boards. 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun #ifdef CONFIG_RAM 52*4882a593Smuzhiyun #define CONFIG_MONITOR_IS_IN_RAM 53*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x40020000 54*4882a593Smuzhiyun #define ENABLE_JFFS 0 55*4882a593Smuzhiyun #else 56*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00000000 57*4882a593Smuzhiyun #define ENABLE_JFFS 1 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define CONFIG_MCFRTC 63*4882a593Smuzhiyun #undef RTC_DEBUG 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Timer */ 66*4882a593Smuzhiyun #define CONFIG_MCFTMR 67*4882a593Smuzhiyun #undef CONFIG_MCFPIT 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* I2C */ 70*4882a593Smuzhiyun #define CONFIG_SYS_I2C 71*4882a593Smuzhiyun #define CONFIG_SYS_I2C_FSL 72*4882a593Smuzhiyun #define CONFIG_SYS_FSL_I2C_SPEED 80000 73*4882a593Smuzhiyun #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 74*4882a593Smuzhiyun #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 75*4882a593Smuzhiyun #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * Defines processor clock - important for correct timings concerning serial 79*4882a593Smuzhiyun * interface etc. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_SYS_CLK 80000000 83*4882a593Smuzhiyun #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) 84*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 87*4882a593Smuzhiyun #define CONFIG_SYS_CORE_SRAM 0x80000000 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define CONFIG_SYS_UNIFY_CACHE 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * Define baudrate for UART1 (console output, tftp, ...) 93*4882a593Smuzhiyun * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud 94*4882a593Smuzhiyun * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected 95*4882a593Smuzhiyun * in u-boot command interface 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CONFIG_MCFUART 99*4882a593Smuzhiyun #define CONFIG_SYS_UART_PORT (2) 100*4882a593Smuzhiyun #define CONFIG_SYS_UART2_ALT3_GPIO 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * Watchdog configuration; Watchdog is disabled for running from RAM 104*4882a593Smuzhiyun * and set to highest possible value else. Beware there is no check 105*4882a593Smuzhiyun * in the watchdog code to validate the timeout value set here! 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #ifndef CONFIG_MONITOR_IS_IN_RAM 109*4882a593Smuzhiyun #define CONFIG_WATCHDOG 110*4882a593Smuzhiyun #define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ 111*4882a593Smuzhiyun #endif 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Configuration for environment 115*4882a593Smuzhiyun * Environment is located in the last sector of the flash 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #ifndef CONFIG_MONITOR_IS_IN_RAM 119*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x1FF8000 120*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x8000 121*4882a593Smuzhiyun #else 122*4882a593Smuzhiyun /* 123*4882a593Smuzhiyun * environment in RAM - This is used to use a single PC-based application 124*4882a593Smuzhiyun * to load an image, load U-Boot, load an environment and then start U-Boot 125*4882a593Smuzhiyun * to execute the commands from the environment. Feedback is done via setting 126*4882a593Smuzhiyun * and reading memory locations. 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun #define CONFIG_ENV_ADDR 0x40060000 129*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x8000 130*4882a593Smuzhiyun #endif 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* here we put our FPGA configuration... */ 133*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 1 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* Define user parameters that have to be customized most likely */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* AUTOBOOT settings - booting images automatically by u-boot after power on */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* 140*4882a593Smuzhiyun * The following settings will be contained in the environment block ; if you 141*4882a593Smuzhiyun * want to use a neutral environment all those settings can be manually set in 142*4882a593Smuzhiyun * u-boot: 'set' command 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 146*4882a593Smuzhiyun "loaderversion=11\0" \ 147*4882a593Smuzhiyun "card_id="__stringify(ASTRO_ID)"\0" \ 148*4882a593Smuzhiyun "alterafile=0\0" \ 149*4882a593Smuzhiyun "xilinxfile=0\0" \ 150*4882a593Smuzhiyun "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ 151*4882a593Smuzhiyun "fpga load 0 0x41000000 $filesize\0" \ 152*4882a593Smuzhiyun "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ 153*4882a593Smuzhiyun "fpga load 1 0x41000000 $filesize\0" \ 154*4882a593Smuzhiyun "env_default=1\0" \ 155*4882a593Smuzhiyun "env_check=if test $env_default -eq 1;"\ 156*4882a593Smuzhiyun " then setenv env_default 0;saveenv;fi\0" 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* 159*4882a593Smuzhiyun * "update" is a non-standard command that has to be supplied 160*4882a593Smuzhiyun * by external update.c; This is not included in mainline because 161*4882a593Smuzhiyun * it needs non-blocking CFI routines. 162*4882a593Smuzhiyun */ 163*4882a593Smuzhiyun #ifdef CONFIG_MONITOR_IS_IN_RAM 164*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ 165*4882a593Smuzhiyun #else 166*4882a593Smuzhiyun #if CONFIG_ASTRO_V532 167*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ 168*4882a593Smuzhiyun "run xilinxload&&run alteraload&&bootm 0x80000;"\ 169*4882a593Smuzhiyun "update;reset" 170*4882a593Smuzhiyun #else 171*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ 172*4882a593Smuzhiyun "run xilinxload&&bootm 0x80000;update;reset" 173*4882a593Smuzhiyun #endif 174*4882a593Smuzhiyun #endif 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* default RAM address for user programs */ 177*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x20000 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define CONFIG_FPGA_COUNT 1 182*4882a593Smuzhiyun #define CONFIG_FPGA_XILINX 183*4882a593Smuzhiyun #define CONFIG_FPGA_SPARTAN3 184*4882a593Smuzhiyun #define CONFIG_FPGA_CYCLON2 185*4882a593Smuzhiyun #define CONFIG_SYS_FPGA_PROG_FEEDBACK 186*4882a593Smuzhiyun #define CONFIG_SYS_FPGA_WAIT 1000 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* End of user parameters to be customized */ 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* Defines memory range for test */ 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x40020000 193*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x41ffffff 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* 196*4882a593Smuzhiyun * Low Level Configuration Settings 197*4882a593Smuzhiyun * (address mappings, register initial values, etc.) 198*4882a593Smuzhiyun * You should know what you are doing if you make changes here. 199*4882a593Smuzhiyun */ 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* Base register address */ 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* System Conf. Reg. & System Protection Reg. */ 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define CONFIG_SYS_SCR 0x0003; 208*4882a593Smuzhiyun #define CONFIG_SYS_SPR 0xffff; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* 211*4882a593Smuzhiyun * Definitions for initial stack pointer and data area (in internal SRAM) 212*4882a593Smuzhiyun */ 213*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 214*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 215*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_CTRL 0x221 216*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 217*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 218*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* 221*4882a593Smuzhiyun * Start addresses for the final memory configuration 222*4882a593Smuzhiyun * (Set up by the startup code) 223*4882a593Smuzhiyun * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 224*4882a593Smuzhiyun */ 225*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x40000000 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* 228*4882a593Smuzhiyun * Chipselect bank definitions 229*4882a593Smuzhiyun * 230*4882a593Smuzhiyun * CS0 - Flash 32MB (first 16MB) 231*4882a593Smuzhiyun * CS1 - Flash 32MB (second half) 232*4882a593Smuzhiyun * CS2 - FPGA 233*4882a593Smuzhiyun * CS3 - FPGA 234*4882a593Smuzhiyun * CS4 - unused 235*4882a593Smuzhiyun * CS5 - unused 236*4882a593Smuzhiyun */ 237*4882a593Smuzhiyun #define CONFIG_SYS_CS0_BASE 0 238*4882a593Smuzhiyun #define CONFIG_SYS_CS0_MASK 0x00ff0001 239*4882a593Smuzhiyun #define CONFIG_SYS_CS0_CTRL 0x00001fc0 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #define CONFIG_SYS_CS1_BASE 0x01000000 242*4882a593Smuzhiyun #define CONFIG_SYS_CS1_MASK 0x00ff0001 243*4882a593Smuzhiyun #define CONFIG_SYS_CS1_CTRL 0x00001fc0 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define CONFIG_SYS_CS2_BASE 0x20000000 246*4882a593Smuzhiyun #define CONFIG_SYS_CS2_MASK 0x00ff0001 247*4882a593Smuzhiyun #define CONFIG_SYS_CS2_CTRL 0x0000fec0 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define CONFIG_SYS_CS3_BASE 0x21000000 250*4882a593Smuzhiyun #define CONFIG_SYS_CS3_MASK 0x00ff0001 251*4882a593Smuzhiyun #define CONFIG_SYS_CS3_CTRL 0x0000fec0 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x00000000 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun #ifdef CONFIG_MONITOR_IS_IN_RAM 256*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 257*4882a593Smuzhiyun #else 258*4882a593Smuzhiyun /* This is mainly used during relocation in start.S */ 259*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 260*4882a593Smuzhiyun #endif 261*4882a593Smuzhiyun /* Reserve 256 kB for Monitor */ 262*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 << 10) 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 265*4882a593Smuzhiyun /* Reserve 128 kB for malloc() */ 266*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (128 << 10) 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* 269*4882a593Smuzhiyun * For booting Linux, the board info and command line data 270*4882a593Smuzhiyun * have to be in the first 8 MB of memory, since this is 271*4882a593Smuzhiyun * the maximum mapped by the Linux kernel during initialization ?? 272*4882a593Smuzhiyun */ 273*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 274*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_SIZE << 20)) 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun /* FLASH organization */ 277*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 278*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 259 279*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 1 282*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 1 283*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_SIZE 0x2000000 284*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_PROTECTION 1 285*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 286*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define LDS_BOARD_TEXT \ 289*4882a593Smuzhiyun . = DEFINED(env_offset) ? env_offset : .; \ 290*4882a593Smuzhiyun env/embedded.o(.text*) 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun #if ENABLE_JFFS 293*4882a593Smuzhiyun /* JFFS Partition offset set */ 294*4882a593Smuzhiyun #define CONFIG_SYS_JFFS2_FIRST_BANK 0 295*4882a593Smuzhiyun #define CONFIG_SYS_JFFS2_NUM_BANKS 1 296*4882a593Smuzhiyun /* 512k reserved for u-boot */ 297*4882a593Smuzhiyun #define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 298*4882a593Smuzhiyun #endif 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* Cache Configuration */ 301*4882a593Smuzhiyun #define CONFIG_SYS_CACHELINE_SIZE 16 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 304*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - 8) 305*4882a593Smuzhiyun #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 306*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - 4) 307*4882a593Smuzhiyun #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 308*4882a593Smuzhiyun #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 309*4882a593Smuzhiyun CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 310*4882a593Smuzhiyun CF_ACR_EN | CF_ACR_SM_ALL) 311*4882a593Smuzhiyun #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 312*4882a593Smuzhiyun CF_CACR_DCM_P) 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun #endif /* _CONFIG_ASTRO_MCF5373L_H */ 315