1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 3*4882a593Smuzhiyun * (C) Copyright 2014 4*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on: 7*4882a593Smuzhiyun * Copyright (C) 2012 Freescale Semiconductor, Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Configuration settings for the Freescale i.MX6Q SabreSD board. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef __ARISTAINETOS_COMMON_CONFIG_H 14*4882a593Smuzhiyun #define __ARISTAINETOS_COMMON_CONFIG_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include "mx6_common.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_MACH_TYPE 4501 19*4882a593Smuzhiyun #define CONFIG_MMCROOT "/dev/mmcblk0p1" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Size of malloc() pool */ 22*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_MXC_UART 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* MMC Configs */ 27*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR 0 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_FEC_MXC 30*4882a593Smuzhiyun #define CONFIG_MII 31*4882a593Smuzhiyun #define IMX_FEC_BASE ENET_BASE_ADDR 32*4882a593Smuzhiyun #define CONFIG_ETHPRIME "FEC" 33*4882a593Smuzhiyun #define CONFIG_FEC_MXC_PHYADDR 0 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_MTD 36*4882a593Smuzhiyun #define CONFIG_MXC_SPI 37*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 20000000 38*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 39*4882a593Smuzhiyun #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 42*4882a593Smuzhiyun "script=u-boot.scr\0" \ 43*4882a593Smuzhiyun "fit_file=/boot/system.itb\0" \ 44*4882a593Smuzhiyun "loadaddr=0x12000000\0" \ 45*4882a593Smuzhiyun "fit_addr_r=0x14000000\0" \ 46*4882a593Smuzhiyun "uboot=/boot/u-boot.imx\0" \ 47*4882a593Smuzhiyun "uboot_sz=d0000\0" \ 48*4882a593Smuzhiyun "rescue_sys_addr=f0000\0" \ 49*4882a593Smuzhiyun "rescue_sys_length=f10000\0" \ 50*4882a593Smuzhiyun "panel=lb07wv8\0" \ 51*4882a593Smuzhiyun "splashpos=m,m\0" \ 52*4882a593Smuzhiyun "console=" CONSOLE_DEV "\0" \ 53*4882a593Smuzhiyun "fdt_high=0xffffffff\0" \ 54*4882a593Smuzhiyun "initrd_high=0xffffffff\0" \ 55*4882a593Smuzhiyun "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 56*4882a593Smuzhiyun "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ 57*4882a593Smuzhiyun "default ${board_type}\0" \ 58*4882a593Smuzhiyun "get_env=mw ${loadaddr} 0 0x20000;" \ 59*4882a593Smuzhiyun "mmc rescan;" \ 60*4882a593Smuzhiyun "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ 61*4882a593Smuzhiyun "env import -t ${loadaddr}\0" \ 62*4882a593Smuzhiyun "default_env=mw ${loadaddr} 0 0x20000;" \ 63*4882a593Smuzhiyun "env export -t ${loadaddr} serial# ethaddr eth1addr " \ 64*4882a593Smuzhiyun "board_type panel;" \ 65*4882a593Smuzhiyun "env default -a;" \ 66*4882a593Smuzhiyun "env import -t ${loadaddr}\0" \ 67*4882a593Smuzhiyun "loadbootscript=" \ 68*4882a593Smuzhiyun "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 69*4882a593Smuzhiyun "bootscript=echo Running bootscript from mmc ...; " \ 70*4882a593Smuzhiyun "source\0" \ 71*4882a593Smuzhiyun "mmcpart=1\0" \ 72*4882a593Smuzhiyun "mmcdev=0\0" \ 73*4882a593Smuzhiyun "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 74*4882a593Smuzhiyun "mmcargs=setenv bootargs console=${console},${baudrate} " \ 75*4882a593Smuzhiyun "root=${mmcroot}\0" \ 76*4882a593Smuzhiyun "mmcboot=echo Booting from mmc ...; " \ 77*4882a593Smuzhiyun "run mmcargs addmtd addmisc set_fit_default;" \ 78*4882a593Smuzhiyun "bootm ${fit_addr_r}\0" \ 79*4882a593Smuzhiyun "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ 80*4882a593Smuzhiyun "${fit_file}\0" \ 81*4882a593Smuzhiyun "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ 82*4882a593Smuzhiyun "${uboot}\0" \ 83*4882a593Smuzhiyun "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ 84*4882a593Smuzhiyun "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ 85*4882a593Smuzhiyun "setexpr uboot_maxsize ${uboot_sz} - 400;" \ 86*4882a593Smuzhiyun "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ 87*4882a593Smuzhiyun "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ 88*4882a593Smuzhiyun "sf write ${loadaddr} 400 ${filesize};" \ 89*4882a593Smuzhiyun "sf read ${cmp_buf} 400 ${uboot_sz};" \ 90*4882a593Smuzhiyun "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ 91*4882a593Smuzhiyun "ubiboot=echo Booting from ubi ...; " \ 92*4882a593Smuzhiyun "run ubiargs addmtd addmisc set_fit_default;" \ 93*4882a593Smuzhiyun "bootm ${fit_addr_r}\0" \ 94*4882a593Smuzhiyun "rescueargs=setenv bootargs console=${console},${baudrate} " \ 95*4882a593Smuzhiyun "root=/dev/ram rw\0 " \ 96*4882a593Smuzhiyun "rescueboot=echo Booting rescue system from NOR ...; " \ 97*4882a593Smuzhiyun "run rescueargs addmtd addmisc set_fit_default;" \ 98*4882a593Smuzhiyun "bootm ${fit_addr_r}\0" \ 99*4882a593Smuzhiyun "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ 100*4882a593Smuzhiyun "${rescue_sys_length}; imi ${fit_addr_r}\0" \ 101*4882a593Smuzhiyun CONFIG_EXTRA_ENV_BOARD_SETTINGS 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 104*4882a593Smuzhiyun "mmc dev ${mmcdev};" \ 105*4882a593Smuzhiyun "if mmc rescan; then " \ 106*4882a593Smuzhiyun "if run loadbootscript; then " \ 107*4882a593Smuzhiyun "run bootscript; " \ 108*4882a593Smuzhiyun "else " \ 109*4882a593Smuzhiyun "if run mmc_load_fit; then " \ 110*4882a593Smuzhiyun "run mmcboot; " \ 111*4882a593Smuzhiyun "else " \ 112*4882a593Smuzhiyun "if run ubifs_load_fit; then " \ 113*4882a593Smuzhiyun "run ubiboot; " \ 114*4882a593Smuzhiyun "else " \ 115*4882a593Smuzhiyun "if run rescue_load_fit; then " \ 116*4882a593Smuzhiyun "run rescueboot; " \ 117*4882a593Smuzhiyun "else " \ 118*4882a593Smuzhiyun "echo RESCUE SYSTEM BOOT " \ 119*4882a593Smuzhiyun "FAILURE;" \ 120*4882a593Smuzhiyun "fi; " \ 121*4882a593Smuzhiyun "fi; " \ 122*4882a593Smuzhiyun "fi; " \ 123*4882a593Smuzhiyun "fi; " \ 124*4882a593Smuzhiyun "else " \ 125*4882a593Smuzhiyun "if run ubifs_load_fit; then " \ 126*4882a593Smuzhiyun "run ubiboot; " \ 127*4882a593Smuzhiyun "else " \ 128*4882a593Smuzhiyun "if run rescue_load_fit; then " \ 129*4882a593Smuzhiyun "run rescueboot; " \ 130*4882a593Smuzhiyun "else " \ 131*4882a593Smuzhiyun "echo RESCUE SYSTEM BOOT FAILURE;" \ 132*4882a593Smuzhiyun "fi; " \ 133*4882a593Smuzhiyun "fi; " \ 134*4882a593Smuzhiyun "fi" 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define CONFIG_ARP_TIMEOUT 200UL 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 139*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) 140*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Physical Memory Map */ 143*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 144*4882a593Smuzhiyun #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 147*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 148*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET \ 151*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 152*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 153*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun /* Environment organization */ 156*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (12 * 1024) 157*4882a593Smuzhiyun #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 158*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 159*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 160*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 161*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 162*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (0x010000) 163*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (0x0d0000) 164*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND (0x0e0000) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USDHC_NUM 2 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* I2C */ 169*4882a593Smuzhiyun #define CONFIG_SYS_I2C 170*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 171*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 172*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 173*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 174*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 175*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x7f 176*4882a593Smuzhiyun #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* NAND stuff */ 179*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 180*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x40000000 181*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 182*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* DMA stuff, needed for GPMI/MXS NAND support */ 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* RTC */ 187*4882a593Smuzhiyun #define CONFIG_SYS_I2C_RTC_ADDR 0x68 188*4882a593Smuzhiyun #define CONFIG_SYS_RTC_BUS_NUM 2 189*4882a593Smuzhiyun #define CONFIG_RTC_M41T11 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* USB Configs */ 192*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 193*4882a593Smuzhiyun #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 194*4882a593Smuzhiyun #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 195*4882a593Smuzhiyun #define CONFIG_MXC_USB_FLAGS 0 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* UBI support */ 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define CONFIG_HW_WATCHDOG 200*4882a593Smuzhiyun #define CONFIG_IMX_WATCHDOG 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* Framebuffer */ 203*4882a593Smuzhiyun #define CONFIG_VIDEO_IPUV3 204*4882a593Smuzhiyun /* check this console not needed, after test remove it */ 205*4882a593Smuzhiyun #define CONFIG_VIDEO_BMP_RLE8 206*4882a593Smuzhiyun #define CONFIG_SPLASH_SCREEN 207*4882a593Smuzhiyun #define CONFIG_SPLASH_SCREEN_ALIGN 208*4882a593Smuzhiyun #define CONFIG_BMP_16BPP 209*4882a593Smuzhiyun #define CONFIG_VIDEO_LOGO 210*4882a593Smuzhiyun #define CONFIG_VIDEO_BMP_LOGO 211*4882a593Smuzhiyun #define CONFIG_IPUV3_CLK 198000000 212*4882a593Smuzhiyun #define CONFIG_IMX_VIDEO_SKIP 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define CONFIG_PWM_IMX 215*4882a593Smuzhiyun #define CONFIG_IMX6_PWM_PER_CLK 66000000 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun #endif /* __ARISTAINETOS_COMMON_CONFIG_H */ 218