1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Alpha Project AP-SH4A-4A board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __AP_SH4A_4A_H 10*4882a593Smuzhiyun #define __AP_SH4A_4A_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7734 1 13*4882a593Smuzhiyun #define CONFIG_AP_SH4A_4A 1 14*4882a593Smuzhiyun #define CONFIG_400MHZ_MODE 1 15*4882a593Smuzhiyun /* #define CONFIG_533MHZ_MODE 1 */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8BFC0000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 20*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Ether */ 23*4882a593Smuzhiyun #define CONFIG_SH_ETHER 1 24*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT (0) 25*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 26*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII) 27*4882a593Smuzhiyun #define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */ 28*4882a593Smuzhiyun #define CONFIG_BITBANGMII 29*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* undef to save memory */ 32*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 33*4882a593Smuzhiyun /* Monitor Command Prompt */ 34*4882a593Smuzhiyun /* Buffer size for Console output */ 35*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 36*4882a593Smuzhiyun /* List of legal baudrate settings for this board */ 37*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* SCIF */ 40*4882a593Smuzhiyun #define CONFIG_SCIF 1 41*4882a593Smuzhiyun #define CONFIG_CONS_SCIF4 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Suppress display of console information at boot */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* SDRAM */ 46*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (0x88000000) 47*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 48*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 51*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE) 52*4882a593Smuzhiyun /* Enable alternate, more extensive, memory test */ 53*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 54*4882a593Smuzhiyun /* Scratch address used by the alternate memory test */ 55*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Enable temporary baudrate change while serial download */ 58*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* FLASH */ 61*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 1 62*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 63*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 64*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO 65*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (0xA0000000) 66*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 512 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 69*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 70*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Timeout for Flash erase operations (in ms) */ 73*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 74*4882a593Smuzhiyun /* Timeout for Flash write operations (in ms) */ 75*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 76*4882a593Smuzhiyun /* Timeout for Flash set sector lock bit operations (in ms) */ 77*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 78*4882a593Smuzhiyun /* Timeout for Flash clear lock bit operations (in ms) */ 79*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * Use hardware flash sectors protection instead 83*4882a593Smuzhiyun * of U-Boot software protection 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_PROTECTION 86*4882a593Smuzhiyun #undef CONFIG_SYS_DIRECT_FLASH_TFTP 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 89*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 90*4882a593Smuzhiyun /* Monitor size */ 91*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 92*4882a593Smuzhiyun /* Size of DRAM reserved for malloc() use */ 93*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 94*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* ENV setting */ 97*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 98*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 99*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 100*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 101*4882a593Smuzhiyun /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 102*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 103*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Board Clock */ 106*4882a593Smuzhiyun #if defined(CONFIG_400MHZ_MODE) 107*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 50000000 108*4882a593Smuzhiyun #else 109*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 44444444 110*4882a593Smuzhiyun #endif 111*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 112*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 113*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #endif /* __AP_SH4A_4A_H */ 116