1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Sysam AMCORE board configuration 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2016 Angelo Dureghello <angelo@sysam.it> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __AMCORE_CONFIG_H 10*4882a593Smuzhiyun #define __AMCORE_CONFIG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_AMCORE 13*4882a593Smuzhiyun #define CONFIG_HOSTNAME AMCORE 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_MCFTMR 16*4882a593Smuzhiyun #define CONFIG_MCFUART 17*4882a593Smuzhiyun #define CONFIG_SYS_UART_PORT 0 18*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "bootm ffc20000" 21*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 22*4882a593Smuzhiyun "upgrade_uboot=loady; " \ 23*4882a593Smuzhiyun "protect off 0xffc00000 0xffc1ffff; " \ 24*4882a593Smuzhiyun "erase 0xffc00000 0xffc1ffff; " \ 25*4882a593Smuzhiyun "cp.b 0x20000 0xffc00000 ${filesize}\0" \ 26*4882a593Smuzhiyun "upgrade_kernel=loady; " \ 27*4882a593Smuzhiyun "erase 0xffc20000 0xffefffff; " \ 28*4882a593Smuzhiyun "cp.b 0x20000 0xffc20000 ${filesize}\0" \ 29*4882a593Smuzhiyun "upgrade_jffs2=loady; " \ 30*4882a593Smuzhiyun "erase 0xfff00000 0xffffffff; " \ 31*4882a593Smuzhiyun "cp.b 0x20000 0xfff00000 ${filesize}\0" 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* undef to save memory */ 34*4882a593Smuzhiyun #undef CONFIG_SYS_LONGHELP 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 37*4882a593Smuzhiyun #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x0 42*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x1000000 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_SYS_HZ 1000 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_SYS_CLK 45000000 47*4882a593Smuzhiyun #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) 48*4882a593Smuzhiyun /* Register Base Addrs */ 49*4882a593Smuzhiyun #define CONFIG_SYS_MBAR 0x10000000 50*4882a593Smuzhiyun /* Definitions for initial stack pointer and data area (in DPRAM) */ 51*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 52*4882a593Smuzhiyun /* size of internal SRAM */ 53*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 54*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 55*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 56*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x00000000 59*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x1000000 60*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0xffc00000 61*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 62*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 1024 63*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 66*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 67*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 68*4882a593Smuzhiyun /* amcore design has flash data bytes wired swapped */ 69*4882a593Smuzhiyun #define CONFIG_SYS_WRITE_SWAPPED_DATA 70*4882a593Smuzhiyun /* reserve 128-4KB */ 71*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 72*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) 73*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 74*4882a593Smuzhiyun #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 77*4882a593Smuzhiyun CONFIG_SYS_MONITOR_LEN) 78*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x1000 79*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x1000 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define LDS_BOARD_TEXT \ 82*4882a593Smuzhiyun . = DEFINED(env_offset) ? env_offset : .; \ 83*4882a593Smuzhiyun env/embedded.o(.text*); 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* memory map space for linux boot data */ 86*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 << 20) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* 89*4882a593Smuzhiyun * Cache Configuration 90*4882a593Smuzhiyun * 91*4882a593Smuzhiyun * Special 8K version 3 core cache. 92*4882a593Smuzhiyun * This is a single unified instruction/data cache. 93*4882a593Smuzhiyun * sdram - single region - no masks 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun #define CONFIG_SYS_CACHELINE_SIZE 16 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 98*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - 8) 99*4882a593Smuzhiyun #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 100*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - 4) 101*4882a593Smuzhiyun #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 102*4882a593Smuzhiyun #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ 103*4882a593Smuzhiyun CF_ACR_EN) 104*4882a593Smuzhiyun #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ 105*4882a593Smuzhiyun CF_CACR_EC) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* CS0 - AMD Flash, address 0xffc00000 */ 108*4882a593Smuzhiyun #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) 109*4882a593Smuzhiyun /* 4MB, AA=0,V=1 C/I BIT for errata */ 110*4882a593Smuzhiyun #define CONFIG_SYS_CS0_MASK 0x003f0001 111*4882a593Smuzhiyun /* WS=10, AA=1, PS=16bit (10) */ 112*4882a593Smuzhiyun #define CONFIG_SYS_CS0_CTRL 0x1980 113*4882a593Smuzhiyun /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ 114*4882a593Smuzhiyun #define CONFIG_SYS_CS1_BASE 0x3000 115*4882a593Smuzhiyun #define CONFIG_SYS_CS1_MASK 0x00070001 116*4882a593Smuzhiyun #define CONFIG_SYS_CS1_CTRL 0x0100 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* __AMCORE_CONFIG_H */ 119*4882a593Smuzhiyun 120