1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/alt.h 3*4882a593Smuzhiyun * This file is alt board configuration. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __ALT_H 11*4882a593Smuzhiyun #define __ALT_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #undef DEBUG 14*4882a593Smuzhiyun #define CONFIG_R8A7794 15*4882a593Smuzhiyun #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "rcar-gen2-common.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x70000000 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xE6304000 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 26*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 27*4882a593Smuzhiyun #else 28*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun #define STACK_AREA_SIZE 0xC000 31*4882a593Smuzhiyun #define LOW_LEVEL_MERAM_STACK \ 32*4882a593Smuzhiyun (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* MEMORY */ 35*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_BASE 0x40000000 36*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 37*4882a593Smuzhiyun #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* FLASH */ 40*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_QUAD 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* SH Ether */ 43*4882a593Smuzhiyun #define CONFIG_SH_ETHER 44*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT 0 45*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR 0x1 46*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 47*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_WRITEBACK 48*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_INVALIDATE 49*4882a593Smuzhiyun #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 50*4882a593Smuzhiyun #define CONFIG_BITBANGMII 51*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Board Clock */ 54*4882a593Smuzhiyun #define RMOBILE_XTAL_CLK 20000000u 55*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 56*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 57*4882a593Smuzhiyun #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 58*4882a593Smuzhiyun #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* i2c */ 63*4882a593Smuzhiyun #define CONFIG_SYS_I2C 64*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH 65*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x7F 66*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 67*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED0 400000 68*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED1 400000 69*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED2 400000 70*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_HIGH 4 71*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_LOW 5 72*4882a593Smuzhiyun #define CONFIG_SH_I2C_CLOCK 10000000 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* USB */ 77*4882a593Smuzhiyun #define CONFIG_USB_EHCI_RMOBILE 78*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* MMCIF */ 81*4882a593Smuzhiyun #define CONFIG_SH_MMCIF 82*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_ADDR 0xee200000 83*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_CLK 48000000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Module stop status bits */ 86*4882a593Smuzhiyun /* INTC-RT */ 87*4882a593Smuzhiyun #define CONFIG_SMSTP0_ENA 0x00400000 88*4882a593Smuzhiyun /* MSIF */ 89*4882a593Smuzhiyun #define CONFIG_SMSTP2_ENA 0x00002000 90*4882a593Smuzhiyun /* INTC-SYS, IRQC */ 91*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 92*4882a593Smuzhiyun /* SCIF2 */ 93*4882a593Smuzhiyun #define CONFIG_SMSTP7_ENA 0x00080000 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* SDHI */ 96*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 97500000 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif /* __ALT_H */ 99