1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Renesas Solutions Migo-R board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MIGO_R_H 10*4882a593Smuzhiyun #define __MIGO_R_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7722 1 13*4882a593Smuzhiyun #define CONFIG_MIGO_R 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 16*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* SMC9111 */ 19*4882a593Smuzhiyun #define CONFIG_SMC91111 20*4882a593Smuzhiyun #define CONFIG_SMC91111_BASE (0xB0000000) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* MEMORY */ 23*4882a593Smuzhiyun #define MIGO_R_SDRAM_BASE (0x8C000000) 24*4882a593Smuzhiyun #define MIGO_R_FLASH_BASE_1 (0xA0000000) 25*4882a593Smuzhiyun #define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 28*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 29*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 30*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* SCIF */ 33*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) 36*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Enable alternate, more extensive, memory test */ 39*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 40*4882a593Smuzhiyun /* Scratch address used by the alternate memory test */ 41*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Enable temporary baudrate change while serial download */ 44*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) 47*4882a593Smuzhiyun /* maybe more, but if so u-boot doesn't know about it... */ 48*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 49*4882a593Smuzhiyun /* default load address for scripts ?!? */ 50*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 53*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) 54*4882a593Smuzhiyun /* Monitor size */ 55*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 56*4882a593Smuzhiyun /* Size of DRAM reserved for malloc() use */ 57*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 58*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* FLASH */ 61*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 62*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 63*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 64*4882a593Smuzhiyun /* print 'E' for empty sector on flinfo */ 65*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO 66*4882a593Smuzhiyun /* Physical start address of Flash memory */ 67*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) 68*4882a593Smuzhiyun /* Max number of sectors on each Flash chip */ 69*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 512 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ 72*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 73*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Timeout for Flash erase operations (in ms) */ 76*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 77*4882a593Smuzhiyun /* Timeout for Flash write operations (in ms) */ 78*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 79*4882a593Smuzhiyun /* Timeout for Flash set sector lock bit operations (in ms) */ 80*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 81*4882a593Smuzhiyun /* Timeout for Flash clear lock bit operations (in ms) */ 82*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Use hardware flash sectors protection instead of U-Boot software protection */ 85*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_PROTECTION 86*4882a593Smuzhiyun #undef CONFIG_SYS_DIRECT_FLASH_TFTP 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* ENV setting */ 89*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 90*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 91*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 92*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 93*4882a593Smuzhiyun /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 94*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 95*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Board Clock */ 98*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 33333333 99*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 100*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 101*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /* __MIGO_R_H */ 104