xref: /OK3568_Linux_fs/u-boot/include/configs/MCR3000.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2010-2017 CS Systemes d'Information
3*4882a593Smuzhiyun  * Christophe Leroy <christophe.leroy@c-s.fr>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __CONFIG_H
9*4882a593Smuzhiyun #define __CONFIG_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /* High Level Configuration Options */
12*4882a593Smuzhiyun #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
13*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R		1	/* Call misc_init_r	*/
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS					\
16*4882a593Smuzhiyun 	"sdram_type=SDRAM\0"						\
17*4882a593Smuzhiyun 	"flash_type=AM29LV160DB\0"					\
18*4882a593Smuzhiyun 	"loadaddr=0x400000\0"						\
19*4882a593Smuzhiyun 	"filename=uImage.lzma\0"					\
20*4882a593Smuzhiyun 	"nfsroot=/opt/ofs\0"						\
21*4882a593Smuzhiyun 	"dhcp_ip=ip=:::::eth0:dhcp\0"					\
22*4882a593Smuzhiyun 	"console_args=console=ttyCPM0,115200N8\0"			\
23*4882a593Smuzhiyun 	"flashboot=setenv bootargs "					\
24*4882a593Smuzhiyun 		"${console_args} "					\
25*4882a593Smuzhiyun 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"	\
26*4882a593Smuzhiyun 		"mcr3k:eth0:off;"					\
27*4882a593Smuzhiyun 		"${ofl_args}; "						\
28*4882a593Smuzhiyun 		"bootm 0x04060000 - 0x04050000\0"			\
29*4882a593Smuzhiyun 	"tftpboot=setenv bootargs "					\
30*4882a593Smuzhiyun 		"${console_args} "					\
31*4882a593Smuzhiyun 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"	\
32*4882a593Smuzhiyun 		"mcr3k:eth0:off "					\
33*4882a593Smuzhiyun 		"${ofl_args}; "						\
34*4882a593Smuzhiyun 		"tftp ${loadaddr} ${filename};"				\
35*4882a593Smuzhiyun 		"tftp 0xf00000 mcr3000.dtb;"				\
36*4882a593Smuzhiyun 		"bootm ${loadaddr} - 0xf00000\0"			\
37*4882a593Smuzhiyun 	"netboot=dhcp ${loadaddr} ${filename};"				\
38*4882a593Smuzhiyun 		"tftp 0xf00000 mcr3000.dtb;"				\
39*4882a593Smuzhiyun 		"setenv bootargs "					\
40*4882a593Smuzhiyun 		"root=/dev/nfs rw "					\
41*4882a593Smuzhiyun 		"${console_args} "					\
42*4882a593Smuzhiyun 		"${dhcp_ip};"						\
43*4882a593Smuzhiyun 		"bootm ${loadaddr} - 0xf00000\0"			\
44*4882a593Smuzhiyun 	"nfsboot=setenv bootargs "					\
45*4882a593Smuzhiyun 		"root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} "	\
46*4882a593Smuzhiyun 		"${console_args} "					\
47*4882a593Smuzhiyun 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:"	\
48*4882a593Smuzhiyun 		"mcr3k:eth0:off;"					\
49*4882a593Smuzhiyun 		"bootm 0x04060000 - 0x04050000\0"			\
50*4882a593Smuzhiyun 	"dhcpboot=dhcp ${loadaddr} ${filename};"			\
51*4882a593Smuzhiyun 		"tftp 0xf00000 mcr3000.dtb;"				\
52*4882a593Smuzhiyun 		"setenv bootargs "					\
53*4882a593Smuzhiyun 		"${console_args} "					\
54*4882a593Smuzhiyun 		"${dhcp_ip} "						\
55*4882a593Smuzhiyun 		"${ofl_args}; "						\
56*4882a593Smuzhiyun 		"bootm ${loadaddr} - 0xf00000\0"
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define CONFIG_BOOTDELAY		5
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #define CONFIG_IPADDR			192.168.0.3
61*4882a593Smuzhiyun #define CONFIG_SERVERIP			192.168.0.1
62*4882a593Smuzhiyun #define CONFIG_NETMASK			255.0.0.0
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND		"run flashboot"
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
67*4882a593Smuzhiyun #undef	CONFIG_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define CONFIG_WATCHDOG		1	/* watchdog enabled */
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /* Miscellaneous configurable options */
72*4882a593Smuzhiyun #define	CONFIG_SYS_LONGHELP
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING		1
75*4882a593Smuzhiyun #ifdef	CONFIG_HUSH_PARSER
76*4882a593Smuzhiyun #define	CONFIG_SYS_PROMPT_HUSH_PS2	"S3K> "
77*4882a593Smuzhiyun #endif
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START	0x00002000
80*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END		0x00800000
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define	CONFIG_SYS_LOAD_ADDR		0x200000
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define	CONFIG_SYS_HZ			1000
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /* Definitions for initial stack pointer and data area (in DPRAM) */
87*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
88*4882a593Smuzhiyun #define	CONFIG_SYS_INIT_RAM_SIZE	0x2f00
89*4882a593Smuzhiyun #define	CONFIG_SYS_GBL_DATA_SIZE	64
90*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
91*4882a593Smuzhiyun 					 CONFIG_SYS_GBL_DATA_SIZE)
92*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */
95*4882a593Smuzhiyun #define	CONFIG_SYS_SDRAM_BASE		0x00000000
96*4882a593Smuzhiyun #define SDRAM_MAX_SIZE			(32 * 1024 * 1024)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /* FLASH organization */
99*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
100*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI		1
101*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER		1
102*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS	1
103*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT	35
104*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT	120000
105*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT	500
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun  * For booting Linux, the board info and command line data
109*4882a593Smuzhiyun  * have to be in the first 8 MB of memory, since this is
110*4882a593Smuzhiyun  * the maximum mapped by the Linux kernel during initialization.
111*4882a593Smuzhiyun  */
112*4882a593Smuzhiyun #define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)
113*4882a593Smuzhiyun #define	CONFIG_SYS_MONITOR_LEN		(256 << 10)
114*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
115*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN		(4096 << 10)
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* Environment Configuration */
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /* environment is in FLASH */
120*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
121*4882a593Smuzhiyun #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
122*4882a593Smuzhiyun #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
123*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
124*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE	1
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* Cache Configuration */
127*4882a593Smuzhiyun #define CONFIG_SYS_CACHELINE_SIZE	16
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /* Ethernet configuration part */
130*4882a593Smuzhiyun #define CONFIG_SYS_DISCOVER_PHY		1
131*4882a593Smuzhiyun #ifdef CONFIG_MPC8XX_FEC
132*4882a593Smuzhiyun #define CONFIG_MII_INIT			1
133*4882a593Smuzhiyun #endif
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /* NAND configuration part */
136*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE	1
137*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MAX_CHIPS	1
138*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE		0x0C000000
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* Internal Definitions */
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* Boot Flags*/
143*4882a593Smuzhiyun #define	BOOTFLAG_COLD			0x01
144*4882a593Smuzhiyun #define BOOTFLAG_WARM			0x02
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #endif /* __CONFIG_H */
147