1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * Hayden Fraser (Hayden.Fraser@freescale.com) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _M5253EVBE_H 9 #define _M5253EVBE_H 10 11 #define CONFIG_M5253EVBE /* define board type */ 12 13 #define CONFIG_MCFTMR 14 15 #define CONFIG_MCFUART 16 #define CONFIG_SYS_UART_PORT (0) 17 18 #undef CONFIG_WATCHDOG /* disable watchdog */ 19 20 21 /* Configuration for environment 22 * Environment is embedded in u-boot in the second sector of the flash 23 */ 24 #ifndef CONFIG_MONITOR_IS_IN_RAM 25 #define CONFIG_ENV_OFFSET 0x4000 26 #define CONFIG_ENV_SECT_SIZE 0x2000 27 #else 28 #define CONFIG_ENV_ADDR 0xffe04000 29 #define CONFIG_ENV_SECT_SIZE 0x2000 30 #endif 31 32 #define LDS_BOARD_TEXT \ 33 . = DEFINED(env_offset) ? env_offset : .; \ 34 env/embedded.o(.text) 35 36 /* 37 * BOOTP options 38 */ 39 #undef CONFIG_BOOTP_BOOTFILESIZE 40 #undef CONFIG_BOOTP_BOOTPATH 41 #undef CONFIG_BOOTP_GATEWAY 42 #undef CONFIG_BOOTP_HOSTNAME 43 44 /* 45 * Command line configuration. 46 */ 47 48 /* ATA */ 49 #define CONFIG_IDE_RESET 1 50 #define CONFIG_IDE_PREINIT 1 51 #define CONFIG_ATAPI 52 #undef CONFIG_LBA48 53 54 #define CONFIG_SYS_IDE_MAXBUS 1 55 #define CONFIG_SYS_IDE_MAXDEVICE 2 56 57 #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) 58 #define CONFIG_SYS_ATA_IDE0_OFFSET 0 59 60 #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ 61 #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ 62 #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ 63 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 64 65 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 66 67 #define CONFIG_SYS_LOAD_ADDR 0x00100000 68 69 #define CONFIG_SYS_MEMTEST_START 0x400 70 #define CONFIG_SYS_MEMTEST_END 0x380000 71 72 #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ 73 #define CONFIG_SYS_FAST_CLK 74 #ifdef CONFIG_SYS_FAST_CLK 75 # define CONFIG_SYS_PLLCR 0x1243E054 76 # define CONFIG_SYS_CLK 140000000 77 #else 78 # define CONFIG_SYS_PLLCR 0x135a4140 79 # define CONFIG_SYS_CLK 70000000 80 #endif 81 82 /* 83 * Low Level Configuration Settings 84 * (address mappings, register initial values, etc.) 85 * You should know what you are doing if you make changes here. 86 */ 87 88 #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ 89 #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ 90 91 /* 92 * Definitions for initial stack pointer and data area (in DPRAM) 93 */ 94 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 95 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 96 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 97 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 98 99 /* 100 * Start addresses for the final memory configuration 101 * (Set up by the startup code) 102 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 103 */ 104 #define CONFIG_SYS_SDRAM_BASE 0x00000000 105 #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */ 106 107 #ifdef CONFIG_MONITOR_IS_IN_RAM 108 #define CONFIG_SYS_MONITOR_BASE 0x20000 109 #else 110 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 111 #endif 112 113 #define CONFIG_SYS_MONITOR_LEN 0x40000 114 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 115 #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) 116 117 /* 118 * For booting Linux, the board info and command line data 119 * have to be in the first 8 MB of memory, since this is 120 * the maximum mapped by the Linux kernel during initialization ?? 121 */ 122 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 123 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 124 125 /* FLASH organization */ 126 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 127 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 128 #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */ 129 #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 130 131 #define CONFIG_SYS_FLASH_CFI 1 132 #define CONFIG_FLASH_CFI_DRIVER 1 133 #define CONFIG_SYS_FLASH_SIZE 0x200000 134 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 135 136 /* Cache Configuration */ 137 #define CONFIG_SYS_CACHELINE_SIZE 16 138 139 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 140 CONFIG_SYS_INIT_RAM_SIZE - 8) 141 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 142 CONFIG_SYS_INIT_RAM_SIZE - 4) 143 #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) 144 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ 145 CF_ADDRMASK(2) | \ 146 CF_ACR_EN | CF_ACR_SM_ALL) 147 #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ 148 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 149 CF_ACR_EN | CF_ACR_SM_ALL) 150 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ 151 CF_CACR_DBWE) 152 153 /* Port configuration */ 154 #define CONFIG_SYS_FECI2C 0xF0 155 156 #define CONFIG_SYS_CS0_BASE 0xFFE00000 157 #define CONFIG_SYS_CS0_MASK 0x001F0021 158 #define CONFIG_SYS_CS0_CTRL 0x00001D80 159 160 /*----------------------------------------------------------------------- 161 * Port configuration 162 */ 163 #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ 164 #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ 165 #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ 166 #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ 167 #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ 168 #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ 169 #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ 170 171 #endif /* _M5253EVB_H */ 172