1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008-2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef COMMON_TIMING_PARAMS_H 8*4882a593Smuzhiyun #define COMMON_TIMING_PARAMS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun typedef struct { 11*4882a593Smuzhiyun /* parameters to constrict */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun unsigned int tckmin_x_ps; 14*4882a593Smuzhiyun unsigned int tckmax_ps; 15*4882a593Smuzhiyun unsigned int trcd_ps; 16*4882a593Smuzhiyun unsigned int trp_ps; 17*4882a593Smuzhiyun unsigned int tras_ps; 18*4882a593Smuzhiyun #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 19*4882a593Smuzhiyun unsigned int taamin_ps; 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_DDR4 23*4882a593Smuzhiyun unsigned int trfc1_ps; 24*4882a593Smuzhiyun unsigned int trfc2_ps; 25*4882a593Smuzhiyun unsigned int trfc4_ps; 26*4882a593Smuzhiyun unsigned int trrds_ps; 27*4882a593Smuzhiyun unsigned int trrdl_ps; 28*4882a593Smuzhiyun unsigned int tccdl_ps; 29*4882a593Smuzhiyun #else 30*4882a593Smuzhiyun unsigned int twtr_ps; /* maximum = 63750 ps */ 31*4882a593Smuzhiyun unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns 32*4882a593Smuzhiyun = 511750 ps */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun unsigned int trrd_ps; /* maximum = 63750 ps */ 35*4882a593Smuzhiyun unsigned int trtp_ps; /* byte 38, spd->trtp */ 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun unsigned int twr_ps; /* maximum = 63750 ps */ 38*4882a593Smuzhiyun unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun unsigned int refresh_rate_ps; 41*4882a593Smuzhiyun unsigned int extended_op_srt; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 44*4882a593Smuzhiyun unsigned int tis_ps; /* byte 32, spd->ca_setup */ 45*4882a593Smuzhiyun unsigned int tih_ps; /* byte 33, spd->ca_hold */ 46*4882a593Smuzhiyun unsigned int tds_ps; /* byte 34, spd->data_setup */ 47*4882a593Smuzhiyun unsigned int tdh_ps; /* byte 35, spd->data_hold */ 48*4882a593Smuzhiyun unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ 49*4882a593Smuzhiyun unsigned int tqhs_ps; /* byte 45, spd->tqhs */ 50*4882a593Smuzhiyun #endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun unsigned int ndimms_present; 53*4882a593Smuzhiyun unsigned int lowest_common_spd_caslat; 54*4882a593Smuzhiyun unsigned int highest_common_derated_caslat; 55*4882a593Smuzhiyun unsigned int additive_latency; 56*4882a593Smuzhiyun unsigned int all_dimms_burst_lengths_bitmask; 57*4882a593Smuzhiyun unsigned int all_dimms_registered; 58*4882a593Smuzhiyun unsigned int all_dimms_unbuffered; 59*4882a593Smuzhiyun unsigned int all_dimms_ecc_capable; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun unsigned long long total_mem; 62*4882a593Smuzhiyun unsigned long long base_address; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* DDR3 RDIMM */ 65*4882a593Smuzhiyun unsigned char rcw[16]; /* Register Control Word 0-15 */ 66*4882a593Smuzhiyun } common_timing_params_t; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69