1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * X-Powers AXP818 Power Management IC driver 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define AXP818_CHIP_ID 0x03 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1 0x10 12*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1_DCDC1_EN (1 << 0) 13*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1_DCDC2_EN (1 << 1) 14*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1_DCDC3_EN (1 << 2) 15*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1_DCDC4_EN (1 << 3) 16*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1_DCDC5_EN (1 << 4) 17*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1_DCDC6_EN (1 << 5) 18*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL1_DCDC7_EN (1 << 6) 19*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2 0x12 20*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_ELDO1_EN (1 << 0) 21*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_ELDO2_EN (1 << 1) 22*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_ELDO3_EN (1 << 2) 23*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_DLDO1_EN (1 << 3) 24*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_DLDO2_EN (1 << 4) 25*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_DLDO3_EN (1 << 5) 26*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_DLDO4_EN (1 << 6) 27*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL2_SW_EN (1 << 7) 28*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL3 0x13 29*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL3_FLDO1_EN (1 << 2) 30*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL3_FLDO2_EN (1 << 3) 31*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL3_FLDO3_EN (1 << 4) 32*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL3_ALDO1_EN (1 << 5) 33*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL3_ALDO2_EN (1 << 6) 34*4882a593Smuzhiyun #define AXP818_OUTPUT_CTRL3_ALDO3_EN (1 << 7) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define AXP818_DLDO1_CTRL 0x15 37*4882a593Smuzhiyun #define AXP818_DLDO2_CTRL 0x16 38*4882a593Smuzhiyun #define AXP818_DLDO3_CTRL 0x17 39*4882a593Smuzhiyun #define AXP818_DLDO4_CTRL 0x18 40*4882a593Smuzhiyun #define AXP818_ELDO1_CTRL 0x19 41*4882a593Smuzhiyun #define AXP818_ELDO2_CTRL 0x1a 42*4882a593Smuzhiyun #define AXP818_ELDO3_CTRL 0x1b 43*4882a593Smuzhiyun #define AXP818_FLDO1_CTRL 0x1c 44*4882a593Smuzhiyun #define AXP818_FLDO2_3_CTRL 0x1d 45*4882a593Smuzhiyun #define AXP818_FLDO2_3_CTRL_FLDO3_VOL (1 << 4) 46*4882a593Smuzhiyun #define AXP818_DCDC1_CTRL 0x20 47*4882a593Smuzhiyun #define AXP818_DCDC2_CTRL 0x21 48*4882a593Smuzhiyun #define AXP818_DCDC3_CTRL 0x22 49*4882a593Smuzhiyun #define AXP818_DCDC4_CTRL 0x23 50*4882a593Smuzhiyun #define AXP818_DCDC5_CTRL 0x24 51*4882a593Smuzhiyun #define AXP818_DCDC6_CTRL 0x25 52*4882a593Smuzhiyun #define AXP818_DCDC7_CTRL 0x26 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define AXP818_ALDO1_CTRL 0x28 55*4882a593Smuzhiyun #define AXP818_ALDO2_CTRL 0x29 56*4882a593Smuzhiyun #define AXP818_ALDO3_CTRL 0x2a 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define AXP818_SHUTDOWN 0x32 59*4882a593Smuzhiyun #define AXP818_SHUTDOWN_POWEROFF (1 << 7) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* For axp_gpio.c */ 62*4882a593Smuzhiyun #define AXP_POWER_STATUS 0x00 63*4882a593Smuzhiyun #define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) 64*4882a593Smuzhiyun #define AXP_VBUS_IPSOUT 0x30 65*4882a593Smuzhiyun #define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) 66*4882a593Smuzhiyun #define AXP_MISC_CTRL 0x8f 67*4882a593Smuzhiyun #define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4) 68*4882a593Smuzhiyun #define AXP_GPIO0_CTRL 0x90 69*4882a593Smuzhiyun #define AXP_GPIO1_CTRL 0x92 70*4882a593Smuzhiyun #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ 71*4882a593Smuzhiyun #define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ 72*4882a593Smuzhiyun #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ 73*4882a593Smuzhiyun #define AXP_GPIO_STATE 0x94 74*4882a593Smuzhiyun #define AXP_GPIO_STATE_OFFSET 0 75