1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun enum axp209_reg { 8*4882a593Smuzhiyun AXP209_POWER_STATUS = 0x00, 9*4882a593Smuzhiyun AXP209_CHIP_VERSION = 0x03, 10*4882a593Smuzhiyun AXP209_OUTPUT_CTRL = 0x12, 11*4882a593Smuzhiyun AXP209_DCDC2_VOLTAGE = 0x23, 12*4882a593Smuzhiyun AXP209_DCDC3_VOLTAGE = 0x27, 13*4882a593Smuzhiyun AXP209_LDO24_VOLTAGE = 0x28, 14*4882a593Smuzhiyun AXP209_LDO3_VOLTAGE = 0x29, 15*4882a593Smuzhiyun AXP209_IRQ_ENABLE1 = 0x40, 16*4882a593Smuzhiyun AXP209_IRQ_ENABLE2 = 0x41, 17*4882a593Smuzhiyun AXP209_IRQ_ENABLE3 = 0x42, 18*4882a593Smuzhiyun AXP209_IRQ_ENABLE4 = 0x43, 19*4882a593Smuzhiyun AXP209_IRQ_ENABLE5 = 0x44, 20*4882a593Smuzhiyun AXP209_IRQ_STATUS5 = 0x4c, 21*4882a593Smuzhiyun AXP209_SHUTDOWN = 0x32, 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AXP209_POWER_STATUS_ON_BY_DC (1 << 0) 25*4882a593Smuzhiyun #define AXP209_POWER_STATUS_VBUS_USABLE (1 << 4) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AXP209_OUTPUT_CTRL_EXTEN (1 << 0) 28*4882a593Smuzhiyun #define AXP209_OUTPUT_CTRL_DCDC3 (1 << 1) 29*4882a593Smuzhiyun #define AXP209_OUTPUT_CTRL_LDO2 (1 << 2) 30*4882a593Smuzhiyun #define AXP209_OUTPUT_CTRL_LDO4 (1 << 3) 31*4882a593Smuzhiyun #define AXP209_OUTPUT_CTRL_DCDC2 (1 << 4) 32*4882a593Smuzhiyun #define AXP209_OUTPUT_CTRL_LDO3 (1 << 6) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AXP209_IRQ5_PEK_UP (1 << 6) 35*4882a593Smuzhiyun #define AXP209_IRQ5_PEK_DOWN (1 << 5) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AXP209_POWEROFF (1 << 7) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* For axp_gpio.c */ 40*4882a593Smuzhiyun #define AXP_POWER_STATUS 0x00 41*4882a593Smuzhiyun #define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) 42*4882a593Smuzhiyun #define AXP_GPIO0_CTRL 0x90 43*4882a593Smuzhiyun #define AXP_GPIO1_CTRL 0x92 44*4882a593Smuzhiyun #define AXP_GPIO2_CTRL 0x93 45*4882a593Smuzhiyun #define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */ 46*4882a593Smuzhiyun #define AXP_GPIO_CTRL_OUTPUT_HIGH 0x01 /* Drive pin high */ 47*4882a593Smuzhiyun #define AXP_GPIO_CTRL_INPUT 0x02 /* Input */ 48*4882a593Smuzhiyun #define AXP_GPIO_STATE 0x94 49*4882a593Smuzhiyun #define AXP_GPIO_STATE_OFFSET 4 50