xref: /OK3568_Linux_fs/u-boot/include/atmel_lcdc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *  Header file for AT91/AT32 LCD Controller
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Data structure and register user interface
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *  Copyright (C) 2007 Atmel Corporation
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #ifndef __ATMEL_LCDC_H__
11*4882a593Smuzhiyun #define __ATMEL_LCDC_H__
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define ATMEL_LCDC_DMABADDR1	0x00
14*4882a593Smuzhiyun #define ATMEL_LCDC_DMABADDR2	0x04
15*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMPT1	0x08
16*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMPT2	0x0c
17*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMADD1	0x10
18*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMADD2	0x14
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define ATMEL_LCDC_DMAFRMCFG	0x18
21*4882a593Smuzhiyun #define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
22*4882a593Smuzhiyun #define	ATMEL_LCDC_BLENGTH_OFFSET	24
23*4882a593Smuzhiyun #define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define ATMEL_LCDC_DMACON	0x1c
26*4882a593Smuzhiyun #define	ATMEL_LCDC_DMAEN	(0x1 << 0)
27*4882a593Smuzhiyun #define	ATMEL_LCDC_DMARST	(0x1 << 1)
28*4882a593Smuzhiyun #define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
29*4882a593Smuzhiyun #define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
30*4882a593Smuzhiyun #define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define ATMEL_LCDC_DMA2DCFG	0x20
33*4882a593Smuzhiyun #define		ATMEL_LCDC_ADDRINC_OFFSET	0
34*4882a593Smuzhiyun #define		ATMEL_LCDC_ADDRINC		(0xffff)
35*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELOFF_OFFSET	24
36*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define ATMEL_LCDC_LCDCON1	0x0800
39*4882a593Smuzhiyun #define	ATMEL_LCDC_BYPASS	(1     <<  0)
40*4882a593Smuzhiyun #define	ATMEL_LCDC_CLKVAL_OFFSET	12
41*4882a593Smuzhiyun #define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
42*4882a593Smuzhiyun #define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define ATMEL_LCDC_LCDCON2	0x0804
45*4882a593Smuzhiyun #define	ATMEL_LCDC_DISTYPE	(3 << 0)
46*4882a593Smuzhiyun #define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
47*4882a593Smuzhiyun #define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
48*4882a593Smuzhiyun #define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
49*4882a593Smuzhiyun #define	ATMEL_LCDC_SCANMOD	(1 << 2)
50*4882a593Smuzhiyun #define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
51*4882a593Smuzhiyun #define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
52*4882a593Smuzhiyun #define	ATMEL_LCDC_IFWIDTH	(3 << 3)
53*4882a593Smuzhiyun #define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
54*4882a593Smuzhiyun #define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
55*4882a593Smuzhiyun #define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
56*4882a593Smuzhiyun #define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
57*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
58*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
59*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
60*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
61*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
62*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
63*4882a593Smuzhiyun #define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
64*4882a593Smuzhiyun #define	ATMEL_LCDC_INVVD	(1 << 8)
65*4882a593Smuzhiyun #define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
66*4882a593Smuzhiyun #define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
67*4882a593Smuzhiyun #define	ATMEL_LCDC_INVFRAME	(1 << 9 )
68*4882a593Smuzhiyun #define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
69*4882a593Smuzhiyun #define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
70*4882a593Smuzhiyun #define	ATMEL_LCDC_INVLINE	(1 << 10)
71*4882a593Smuzhiyun #define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
72*4882a593Smuzhiyun #define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
73*4882a593Smuzhiyun #define	ATMEL_LCDC_INVCLK	(1 << 11)
74*4882a593Smuzhiyun #define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
75*4882a593Smuzhiyun #define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
76*4882a593Smuzhiyun #define	ATMEL_LCDC_INVDVAL	(1 << 12)
77*4882a593Smuzhiyun #define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
78*4882a593Smuzhiyun #define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
79*4882a593Smuzhiyun #define	ATMEL_LCDC_CLKMOD	(1 << 15)
80*4882a593Smuzhiyun #define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
81*4882a593Smuzhiyun #define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
82*4882a593Smuzhiyun #define	ATMEL_LCDC_MEMOR	(1 << 31)
83*4882a593Smuzhiyun #define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
84*4882a593Smuzhiyun #define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define ATMEL_LCDC_TIM1		0x0808
87*4882a593Smuzhiyun #define	ATMEL_LCDC_VFP		(0xffU <<  0)
88*4882a593Smuzhiyun #define	ATMEL_LCDC_VBP_OFFSET		8
89*4882a593Smuzhiyun #define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
90*4882a593Smuzhiyun #define	ATMEL_LCDC_VPW_OFFSET		16
91*4882a593Smuzhiyun #define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
92*4882a593Smuzhiyun #define	ATMEL_LCDC_VHDLY_OFFSET		24
93*4882a593Smuzhiyun #define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define ATMEL_LCDC_TIM2		0x080c
96*4882a593Smuzhiyun #define	ATMEL_LCDC_HBP		(0xffU  <<  0)
97*4882a593Smuzhiyun #define	ATMEL_LCDC_HPW_OFFSET		8
98*4882a593Smuzhiyun #define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
99*4882a593Smuzhiyun #define	ATMEL_LCDC_HFP_OFFSET		21
100*4882a593Smuzhiyun #define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define ATMEL_LCDC_LCDFRMCFG	0x0810
103*4882a593Smuzhiyun #define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
104*4882a593Smuzhiyun #define	ATMEL_LCDC_HOZVAL_OFFSET	21
105*4882a593Smuzhiyun #define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define ATMEL_LCDC_FIFO		0x0814
108*4882a593Smuzhiyun #define	ATMEL_LCDC_FIFOTH	(0xffff)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define ATMEL_LCDC_MVAL		0x0818
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #define ATMEL_LCDC_DP1_2	0x081c
113*4882a593Smuzhiyun #define ATMEL_LCDC_DP4_7	0x0820
114*4882a593Smuzhiyun #define ATMEL_LCDC_DP3_5	0x0824
115*4882a593Smuzhiyun #define ATMEL_LCDC_DP2_3	0x0828
116*4882a593Smuzhiyun #define ATMEL_LCDC_DP5_7	0x082c
117*4882a593Smuzhiyun #define ATMEL_LCDC_DP3_4	0x0830
118*4882a593Smuzhiyun #define ATMEL_LCDC_DP4_5	0x0834
119*4882a593Smuzhiyun #define ATMEL_LCDC_DP6_7	0x0838
120*4882a593Smuzhiyun #define	ATMEL_LCDC_DP1_2_VAL	(0xff)
121*4882a593Smuzhiyun #define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
122*4882a593Smuzhiyun #define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
123*4882a593Smuzhiyun #define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
124*4882a593Smuzhiyun #define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
125*4882a593Smuzhiyun #define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
126*4882a593Smuzhiyun #define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
127*4882a593Smuzhiyun #define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define ATMEL_LCDC_PWRCON	0x083c
130*4882a593Smuzhiyun #define	ATMEL_LCDC_PWR		(1    <<  0)
131*4882a593Smuzhiyun #define	ATMEL_LCDC_GUARDT_OFFSET	1
132*4882a593Smuzhiyun #define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
133*4882a593Smuzhiyun #define	ATMEL_LCDC_BUSY		(1    << 31)
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun #define ATMEL_LCDC_CONTRAST_CTR	0x0840
136*4882a593Smuzhiyun #define	ATMEL_LCDC_PS		(3 << 0)
137*4882a593Smuzhiyun #define		ATMEL_LCDC_PS_DIV1		(0 << 0)
138*4882a593Smuzhiyun #define		ATMEL_LCDC_PS_DIV2		(1 << 0)
139*4882a593Smuzhiyun #define		ATMEL_LCDC_PS_DIV4		(2 << 0)
140*4882a593Smuzhiyun #define		ATMEL_LCDC_PS_DIV8		(3 << 0)
141*4882a593Smuzhiyun #define	ATMEL_LCDC_POL		(1 << 2)
142*4882a593Smuzhiyun #define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
143*4882a593Smuzhiyun #define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
144*4882a593Smuzhiyun #define	ATMEL_LCDC_ENA		(1 << 3)
145*4882a593Smuzhiyun #define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
146*4882a593Smuzhiyun #define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun #define ATMEL_LCDC_CONTRAST_VAL	0x0844
149*4882a593Smuzhiyun #define	ATMEL_LCDC_CVAL	(0xff)
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun #define ATMEL_LCDC_IER		0x0848
152*4882a593Smuzhiyun #define ATMEL_LCDC_IDR		0x084c
153*4882a593Smuzhiyun #define ATMEL_LCDC_IMR		0x0850
154*4882a593Smuzhiyun #define ATMEL_LCDC_ISR		0x0854
155*4882a593Smuzhiyun #define ATMEL_LCDC_ICR		0x0858
156*4882a593Smuzhiyun #define	ATMEL_LCDC_LNI		(1 << 0)
157*4882a593Smuzhiyun #define	ATMEL_LCDC_LSTLNI	(1 << 1)
158*4882a593Smuzhiyun #define	ATMEL_LCDC_EOFI		(1 << 2)
159*4882a593Smuzhiyun #define	ATMEL_LCDC_UFLWI	(1 << 4)
160*4882a593Smuzhiyun #define	ATMEL_LCDC_OWRI		(1 << 5)
161*4882a593Smuzhiyun #define	ATMEL_LCDC_MERI		(1 << 6)
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #endif /* __ATMEL_LCDC_H__ */
166