1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * atmel_lcd.h - Atmel LCD Controller structures 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2001 5*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ATMEL_LCD_H_ 11*4882a593Smuzhiyun #define _ATMEL_LCD_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /** 14*4882a593Smuzhiyun * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * @timing_index: Index of LCD timing to use in device tree node 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun struct atmel_lcd_platdata { 19*4882a593Smuzhiyun int timing_index; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun typedef struct vidinfo { 23*4882a593Smuzhiyun ushort vl_col; /* Number of columns (i.e. 640) */ 24*4882a593Smuzhiyun ushort vl_row; /* Number of rows (i.e. 480) */ 25*4882a593Smuzhiyun ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ 26*4882a593Smuzhiyun u_long vl_clk; /* pixel clock in ps */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* LCD configuration register */ 29*4882a593Smuzhiyun u_long vl_sync; /* Horizontal / vertical sync */ 30*4882a593Smuzhiyun u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 31*4882a593Smuzhiyun u_long vl_tft; /* 0 = passive, 1 = TFT */ 32*4882a593Smuzhiyun u_long vl_cont_pol_low; /* contrast polarity is low */ 33*4882a593Smuzhiyun u_long vl_clk_pol; /* clock polarity */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Horizontal control register. */ 36*4882a593Smuzhiyun u_long vl_hsync_len; /* Length of horizontal sync */ 37*4882a593Smuzhiyun u_long vl_left_margin; /* Time from sync to picture */ 38*4882a593Smuzhiyun u_long vl_right_margin; /* Time from picture to sync */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Vertical control register. */ 41*4882a593Smuzhiyun u_long vl_vsync_len; /* Length of vertical sync */ 42*4882a593Smuzhiyun u_long vl_upper_margin; /* Time from sync to picture */ 43*4882a593Smuzhiyun u_long vl_lower_margin; /* Time from picture to sync */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun u_long mmio; /* Memory mapped registers */ 46*4882a593Smuzhiyun } vidinfo_t; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #endif 49