1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2005 3*4882a593Smuzhiyun * ARM Ltd. 4*4882a593Smuzhiyun * Peter Pearse, <Peter.Pearse@arm.com> 5*4882a593Smuzhiyun * Configuration for ARM Core Modules. 6*4882a593Smuzhiyun * No standalonw port yet available 7*4882a593Smuzhiyun * - this file is included by both integratorap.h & integratorcp.h 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __ARMCOREMODULE_H 13*4882a593Smuzhiyun #define __ARMCOREMODULE_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CM_BASE 0x10000000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* CM registers common to all CMs */ 18*4882a593Smuzhiyun /* Note that observed values after reboot into the ARM Boot Monitor 19*4882a593Smuzhiyun have been used as defaults, rather than the POR values */ 20*4882a593Smuzhiyun #define OS_CTRL 0x0000000C 21*4882a593Smuzhiyun #define CMMASK_REMAP 0x00000005 /* set remap & led */ 22*4882a593Smuzhiyun #define CMMASK_RESET 0x00000008 23*4882a593Smuzhiyun #define OS_LOCK 0x00000014 24*4882a593Smuzhiyun #define CMVAL_LOCK1 0x0000A000 /* locking value */ 25*4882a593Smuzhiyun #define CMVAL_LOCK2 0x0000005F /* locking value */ 26*4882a593Smuzhiyun #define CMVAL_UNLOCK 0x00000000 /* any value != CM_LOCKVAL */ 27*4882a593Smuzhiyun #define OS_SDRAM 0x00000020 28*4882a593Smuzhiyun #define OS_INIT 0x00000024 29*4882a593Smuzhiyun #define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ 30*4882a593Smuzhiyun #define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ 31*4882a593Smuzhiyun #define CMMASK_LOWVEC 0x00000000 /* vectors @ 0x00000000 */ 32*4882a593Smuzhiyun #define CMMASK_LE 0xFFFFFFF7 /* little endian */ 33*4882a593Smuzhiyun #define CMMASK_CMxx6_COMMON 0x00000013 /* Common value for CMxx6 */ 34*4882a593Smuzhiyun /* - observed reset value of */ 35*4882a593Smuzhiyun /* CM926EJ-S */ 36*4882a593Smuzhiyun /* CM1136-EJ-S */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) 39*4882a593Smuzhiyun #define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual */ 40*4882a593Smuzhiyun /* - PLL test clock bypassed */ 41*4882a593Smuzhiyun /* - bus clock ratio 2 */ 42*4882a593Smuzhiyun /* - little endian */ 43*4882a593Smuzhiyun /* - vectors at zero */ 44*4882a593Smuzhiyun #endif /* CM1022xx */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Determine CM characteristics */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #undef CONFIG_CM_MULTIPLE_SSRAM 49*4882a593Smuzhiyun #undef CONFIG_CM_SPD_DETECT 50*4882a593Smuzhiyun #undef CONFIG_CM_REMAP 51*4882a593Smuzhiyun #undef CONFIG_CM_INIT 52*4882a593Smuzhiyun #undef CONFIG_CM_TCRAM 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S) 55*4882a593Smuzhiyun #define CONFIG_CM_MULTIPLE_SSRAM /* CM has multiple SSRAM mapping */ 56*4882a593Smuzhiyun #endif 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Excalibur core module has reduced functionality */ 59*4882a593Smuzhiyun #ifndef CONFIG_CM922T_XA10 60*4882a593Smuzhiyun #define CONFIG_CM_SPD_DETECT /* CM supports SPD query */ 61*4882a593Smuzhiyun #define OS_SPD 0x00000100 /* Address of SPD data */ 62*4882a593Smuzhiyun #define CONFIG_CM_REMAP /* CM supports remapping */ 63*4882a593Smuzhiyun #define CONFIG_CM_INIT /* CM has initialization reg */ 64*4882a593Smuzhiyun #endif /* NOT EXCALIBUR */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #if defined(CONFIG_CM926EJ_S) || defined (CONFIG_CM946E_S) || \ 67*4882a593Smuzhiyun defined(CONFIG_CM966E_S) || defined (CONFIG_CM1026EJ_S) || \ 68*4882a593Smuzhiyun defined(CONFIG_CM1136JF_S) 69*4882a593Smuzhiyun #define CONFIG_CM_TCRAM /* CM has TCRAM */ 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #ifdef CONFIG_CM_SPD_DETECT 73*4882a593Smuzhiyun #define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* __ARMCOREMODULE_H */ 77