1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2002 3*4882a593Smuzhiyun * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <fpga.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ALTERA_H_ 11*4882a593Smuzhiyun #define _ALTERA_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * For the StratixV FPGA programming via SPI, the following 15*4882a593Smuzhiyun * information is coded in the 32bit cookie: 16*4882a593Smuzhiyun * Bit 31 ... Bit 0 17*4882a593Smuzhiyun * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define FPGA_COOKIE(bus, dev, config, done) \ 20*4882a593Smuzhiyun (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done)) 21*4882a593Smuzhiyun #define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff) 22*4882a593Smuzhiyun #define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff) 23*4882a593Smuzhiyun #define COOKIE2CONFIG(c) (((c) >> 8) & 0xff) 24*4882a593Smuzhiyun #define COOKIE2DONE(c) ((c) & 0xff) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun enum altera_iface { 27*4882a593Smuzhiyun /* insert all new types after this */ 28*4882a593Smuzhiyun min_altera_iface_type, 29*4882a593Smuzhiyun /* serial data and external clock */ 30*4882a593Smuzhiyun passive_serial, 31*4882a593Smuzhiyun /* parallel data */ 32*4882a593Smuzhiyun passive_parallel_synchronous, 33*4882a593Smuzhiyun /* parallel data */ 34*4882a593Smuzhiyun passive_parallel_asynchronous, 35*4882a593Smuzhiyun /* serial data w/ internal clock (not used) */ 36*4882a593Smuzhiyun passive_serial_asynchronous, 37*4882a593Smuzhiyun /* jtag/tap serial (not used ) */ 38*4882a593Smuzhiyun altera_jtag_mode, 39*4882a593Smuzhiyun /* fast passive parallel (FPP) */ 40*4882a593Smuzhiyun fast_passive_parallel, 41*4882a593Smuzhiyun /* fast passive parallel with security (FPPS) */ 42*4882a593Smuzhiyun fast_passive_parallel_security, 43*4882a593Smuzhiyun /* insert all new types before this */ 44*4882a593Smuzhiyun max_altera_iface_type, 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun enum altera_family { 48*4882a593Smuzhiyun /* insert all new types after this */ 49*4882a593Smuzhiyun min_altera_type, 50*4882a593Smuzhiyun /* ACEX1K Family */ 51*4882a593Smuzhiyun Altera_ACEX1K, 52*4882a593Smuzhiyun /* CYCLONII Family */ 53*4882a593Smuzhiyun Altera_CYC2, 54*4882a593Smuzhiyun /* StratixII Family */ 55*4882a593Smuzhiyun Altera_StratixII, 56*4882a593Smuzhiyun /* StratixV Family */ 57*4882a593Smuzhiyun Altera_StratixV, 58*4882a593Smuzhiyun /* SoCFPGA Family */ 59*4882a593Smuzhiyun Altera_SoCFPGA, 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Add new models here */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* insert all new types before this */ 64*4882a593Smuzhiyun max_altera_type, 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun typedef struct { 68*4882a593Smuzhiyun /* part type */ 69*4882a593Smuzhiyun enum altera_family family; 70*4882a593Smuzhiyun /* interface type */ 71*4882a593Smuzhiyun enum altera_iface iface; 72*4882a593Smuzhiyun /* bytes of data part can accept */ 73*4882a593Smuzhiyun size_t size; 74*4882a593Smuzhiyun /* interface function table */ 75*4882a593Smuzhiyun void *iface_fns; 76*4882a593Smuzhiyun /* base interface address */ 77*4882a593Smuzhiyun void *base; 78*4882a593Smuzhiyun /* implementation specific cookie */ 79*4882a593Smuzhiyun int cookie; 80*4882a593Smuzhiyun } Altera_desc; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Generic Altera Functions 83*4882a593Smuzhiyun *********************************************************************/ 84*4882a593Smuzhiyun extern int altera_load(Altera_desc *desc, const void *image, size_t size); 85*4882a593Smuzhiyun extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize); 86*4882a593Smuzhiyun extern int altera_info(Altera_desc *desc); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Board specific implementation specific function types 89*4882a593Smuzhiyun *********************************************************************/ 90*4882a593Smuzhiyun typedef int (*Altera_pre_fn)( int cookie ); 91*4882a593Smuzhiyun typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie ); 92*4882a593Smuzhiyun typedef int (*Altera_status_fn)( int cookie ); 93*4882a593Smuzhiyun typedef int (*Altera_done_fn)( int cookie ); 94*4882a593Smuzhiyun typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie ); 95*4882a593Smuzhiyun typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie ); 96*4882a593Smuzhiyun typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie); 97*4882a593Smuzhiyun typedef int (*Altera_abort_fn)( int cookie ); 98*4882a593Smuzhiyun typedef int (*Altera_post_fn)( int cookie ); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun typedef struct { 101*4882a593Smuzhiyun Altera_pre_fn pre; 102*4882a593Smuzhiyun Altera_config_fn config; 103*4882a593Smuzhiyun Altera_status_fn status; 104*4882a593Smuzhiyun Altera_done_fn done; 105*4882a593Smuzhiyun Altera_clk_fn clk; 106*4882a593Smuzhiyun Altera_data_fn data; 107*4882a593Smuzhiyun Altera_write_fn write; 108*4882a593Smuzhiyun Altera_abort_fn abort; 109*4882a593Smuzhiyun Altera_post_fn post; 110*4882a593Smuzhiyun } altera_board_specific_func; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #ifdef CONFIG_FPGA_SOCFPGA 113*4882a593Smuzhiyun int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); 114*4882a593Smuzhiyun #endif 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #ifdef CONFIG_FPGA_STRATIX_V 117*4882a593Smuzhiyun int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size); 118*4882a593Smuzhiyun #endif 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* _ALTERA_H_ */ 121