1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /*
12*4882a593Smuzhiyun * MX7ULP WDOG Register Map
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun struct wdog_regs {
15*4882a593Smuzhiyun u8 cs1;
16*4882a593Smuzhiyun u8 cs2;
17*4882a593Smuzhiyun u16 reserve0;
18*4882a593Smuzhiyun u32 cnt;
19*4882a593Smuzhiyun u32 toval;
20*4882a593Smuzhiyun u32 win;
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
24*4882a593Smuzhiyun #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define REFRESH_WORD0 0xA602 /* 1st refresh word */
28*4882a593Smuzhiyun #define REFRESH_WORD1 0xB480 /* 2nd refresh word */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
31*4882a593Smuzhiyun #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define WDGCS1_WDGE (1<<7)
34*4882a593Smuzhiyun #define WDGCS1_WDGUPDATE (1<<5)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define WDGCS2_FLG (1<<6)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define WDG_BUS_CLK (0x0)
39*4882a593Smuzhiyun #define WDG_LPO_CLK (0x1)
40*4882a593Smuzhiyun #define WDG_32KHZ_CLK (0x2)
41*4882a593Smuzhiyun #define WDG_EXT_CLK (0x3)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
44*4882a593Smuzhiyun
hw_watchdog_set_timeout(u16 val)45*4882a593Smuzhiyun void hw_watchdog_set_timeout(u16 val)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun /* setting timeout value */
48*4882a593Smuzhiyun struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun writel(val, &wdog->toval);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
hw_watchdog_reset(void)53*4882a593Smuzhiyun void hw_watchdog_reset(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun writel(REFRESH_WORD0, &wdog->cnt);
58*4882a593Smuzhiyun writel(REFRESH_WORD1, &wdog->cnt);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
hw_watchdog_init(void)61*4882a593Smuzhiyun void hw_watchdog_init(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun u8 val;
64*4882a593Smuzhiyun struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun writel(UNLOCK_WORD0, &wdog->cnt);
67*4882a593Smuzhiyun writel(UNLOCK_WORD1, &wdog->cnt);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun val = readb(&wdog->cs2);
70*4882a593Smuzhiyun val |= WDGCS2_FLG;
71*4882a593Smuzhiyun writeb(val, &wdog->cs2);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
74*4882a593Smuzhiyun writel(0, &wdog->win);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
77*4882a593Smuzhiyun writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun hw_watchdog_reset();
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
reset_cpu(ulong addr)82*4882a593Smuzhiyun void reset_cpu(ulong addr)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun writel(UNLOCK_WORD0, &wdog->cnt);
87*4882a593Smuzhiyun writel(UNLOCK_WORD1, &wdog->cnt);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun hw_watchdog_set_timeout(5); /* 5ms timeout */
90*4882a593Smuzhiyun writel(0, &wdog->win);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
93*4882a593Smuzhiyun writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun hw_watchdog_reset();
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun while (1);
98*4882a593Smuzhiyun }
99