1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * drivers/watchdog/orion_wdt.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Watchdog driver for Orion/Kirkwood processors
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Authors: Tomas Hlavacek <tmshlvck@gmail.com>
7*4882a593Smuzhiyun * Sylver Bruneau <sylver.bruneau@googlemail.com>
8*4882a593Smuzhiyun * Marek Behun <marek.behun@nic.cz>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
11*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
12*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <common.h>
16*4882a593Smuzhiyun #include <dm.h>
17*4882a593Smuzhiyun #include <wdt.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun #include <asm/arch/cpu.h>
20*4882a593Smuzhiyun #include <asm/arch/soc.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct orion_wdt_priv {
25*4882a593Smuzhiyun void __iomem *reg;
26*4882a593Smuzhiyun int wdt_counter_offset;
27*4882a593Smuzhiyun void __iomem *rstout;
28*4882a593Smuzhiyun void __iomem *rstout_mask;
29*4882a593Smuzhiyun u32 timeout;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define RSTOUT_ENABLE_BIT BIT(8)
33*4882a593Smuzhiyun #define RSTOUT_MASK_BIT BIT(10)
34*4882a593Smuzhiyun #define WDT_ENABLE_BIT BIT(8)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define TIMER_CTRL 0x0000
37*4882a593Smuzhiyun #define TIMER_A370_STATUS 0x04
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
40*4882a593Smuzhiyun #define WDT_A370_EXPIRED BIT(31)
41*4882a593Smuzhiyun
orion_wdt_reset(struct udevice * dev)42*4882a593Smuzhiyun static int orion_wdt_reset(struct udevice *dev)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct orion_wdt_priv *priv = dev_get_priv(dev);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Reload watchdog duration */
47*4882a593Smuzhiyun writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
orion_wdt_start(struct udevice * dev,u64 timeout,ulong flags)52*4882a593Smuzhiyun static int orion_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct orion_wdt_priv *priv = dev_get_priv(dev);
55*4882a593Smuzhiyun u32 reg;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun priv->timeout = (u32) timeout;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Enable the fixed watchdog clock input */
60*4882a593Smuzhiyun reg = readl(priv->reg + TIMER_CTRL);
61*4882a593Smuzhiyun reg |= WDT_AXP_FIXED_ENABLE_BIT;
62*4882a593Smuzhiyun writel(reg, priv->reg + TIMER_CTRL);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Set watchdog duration */
65*4882a593Smuzhiyun writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Clear the watchdog expiration bit */
68*4882a593Smuzhiyun reg = readl(priv->reg + TIMER_A370_STATUS);
69*4882a593Smuzhiyun reg &= ~WDT_A370_EXPIRED;
70*4882a593Smuzhiyun writel(reg, priv->reg + TIMER_A370_STATUS);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Enable watchdog timer */
73*4882a593Smuzhiyun reg = readl(priv->reg + TIMER_CTRL);
74*4882a593Smuzhiyun reg |= WDT_ENABLE_BIT;
75*4882a593Smuzhiyun writel(reg, priv->reg + TIMER_CTRL);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Enable reset on watchdog */
78*4882a593Smuzhiyun reg = readl(priv->rstout);
79*4882a593Smuzhiyun reg |= RSTOUT_ENABLE_BIT;
80*4882a593Smuzhiyun writel(reg, priv->rstout);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun reg = readl(priv->rstout_mask);
83*4882a593Smuzhiyun reg &= ~RSTOUT_MASK_BIT;
84*4882a593Smuzhiyun writel(reg, priv->rstout_mask);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
orion_wdt_stop(struct udevice * dev)89*4882a593Smuzhiyun static int orion_wdt_stop(struct udevice *dev)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct orion_wdt_priv *priv = dev_get_priv(dev);
92*4882a593Smuzhiyun u32 reg;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Disable reset on watchdog */
95*4882a593Smuzhiyun reg = readl(priv->rstout_mask);
96*4882a593Smuzhiyun reg |= RSTOUT_MASK_BIT;
97*4882a593Smuzhiyun writel(reg, priv->rstout_mask);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun reg = readl(priv->rstout);
100*4882a593Smuzhiyun reg &= ~RSTOUT_ENABLE_BIT;
101*4882a593Smuzhiyun writel(reg, priv->rstout);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Disable watchdog timer */
104*4882a593Smuzhiyun reg = readl(priv->reg + TIMER_CTRL);
105*4882a593Smuzhiyun reg &= ~WDT_ENABLE_BIT;
106*4882a593Smuzhiyun writel(reg, priv->reg + TIMER_CTRL);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
save_reg_from_ofdata(struct udevice * dev,int index,void __iomem ** reg,int * offset)111*4882a593Smuzhiyun static inline bool save_reg_from_ofdata(struct udevice *dev, int index,
112*4882a593Smuzhiyun void __iomem **reg, int *offset)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun fdt_addr_t addr;
115*4882a593Smuzhiyun fdt_size_t off;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun addr = fdtdec_get_addr_size_auto_noparent(
118*4882a593Smuzhiyun gd->fdt_blob, dev_of_offset(dev), "reg", index, &off, true);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (addr == FDT_ADDR_T_NONE)
121*4882a593Smuzhiyun return false;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun *reg = (void __iomem *) addr;
124*4882a593Smuzhiyun if (offset)
125*4882a593Smuzhiyun *offset = off;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return true;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
orion_wdt_ofdata_to_platdata(struct udevice * dev)130*4882a593Smuzhiyun static int orion_wdt_ofdata_to_platdata(struct udevice *dev)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct orion_wdt_priv *priv = dev_get_priv(dev);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (!save_reg_from_ofdata(dev, 0, &priv->reg,
135*4882a593Smuzhiyun &priv->wdt_counter_offset))
136*4882a593Smuzhiyun goto err;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun if (!save_reg_from_ofdata(dev, 1, &priv->rstout, NULL))
139*4882a593Smuzhiyun goto err;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL))
142*4882a593Smuzhiyun goto err;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun err:
146*4882a593Smuzhiyun debug("%s: Could not determine Orion wdt IO addresses\n", __func__);
147*4882a593Smuzhiyun return -ENXIO;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
orion_wdt_probe(struct udevice * dev)150*4882a593Smuzhiyun static int orion_wdt_probe(struct udevice *dev)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun debug("%s: Probing wdt%u\n", __func__, dev->seq);
153*4882a593Smuzhiyun orion_wdt_stop(dev);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun static const struct wdt_ops orion_wdt_ops = {
159*4882a593Smuzhiyun .start = orion_wdt_start,
160*4882a593Smuzhiyun .reset = orion_wdt_reset,
161*4882a593Smuzhiyun .stop = orion_wdt_stop,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const struct udevice_id orion_wdt_ids[] = {
165*4882a593Smuzhiyun { .compatible = "marvell,armada-380-wdt" },
166*4882a593Smuzhiyun {}
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun U_BOOT_DRIVER(orion_wdt) = {
170*4882a593Smuzhiyun .name = "orion_wdt",
171*4882a593Smuzhiyun .id = UCLASS_WDT,
172*4882a593Smuzhiyun .of_match = orion_wdt_ids,
173*4882a593Smuzhiyun .probe = orion_wdt_probe,
174*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct orion_wdt_priv),
175*4882a593Smuzhiyun .ofdata_to_platdata = orion_wdt_ofdata_to_platdata,
176*4882a593Smuzhiyun .ops = &orion_wdt_ops,
177*4882a593Smuzhiyun };
178