1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * omap_wdt.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2013
5*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * commit 2d991a164a61858012651e13c59521975504e260
14*4882a593Smuzhiyun * Author: Bill Pemberton <wfp5p@virginia.edu>
15*4882a593Smuzhiyun * Date: Mon Nov 19 13:21:41 2012 -0500
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * watchdog: remove use of __devinit
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * CONFIG_HOTPLUG is going away as an option so __devinit is no longer
20*4882a593Smuzhiyun * needed.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * Author: MontaVista Software, Inc.
23*4882a593Smuzhiyun * <gdavis@mvista.com> or <source@mvista.com>
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * History:
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * 20030527: George G. Davis <gdavis@mvista.com>
28*4882a593Smuzhiyun * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
29*4882a593Smuzhiyun * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
30*4882a593Smuzhiyun * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * Copyright (c) 2004 Texas Instruments.
33*4882a593Smuzhiyun * 1. Modified to support OMAP1610 32-KHz watchdog timer
34*4882a593Smuzhiyun * 2. Ported to 2.6 kernel
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun * Copyright (c) 2005 David Brownell
37*4882a593Smuzhiyun * Use the driver model and standard identifiers; handle bigger timeouts.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include <common.h>
41*4882a593Smuzhiyun #include <watchdog.h>
42*4882a593Smuzhiyun #include <asm/arch/hardware.h>
43*4882a593Smuzhiyun #include <asm/io.h>
44*4882a593Smuzhiyun #include <asm/processor.h>
45*4882a593Smuzhiyun #include <asm/arch/cpu.h>
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Hardware timeout in seconds */
48*4882a593Smuzhiyun #define WDT_HW_TIMEOUT 60
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static unsigned int wdt_trgr_pattern = 0x1234;
51*4882a593Smuzhiyun
hw_watchdog_reset(void)52*4882a593Smuzhiyun void hw_watchdog_reset(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* wait for posted write to complete */
57*4882a593Smuzhiyun while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR)
58*4882a593Smuzhiyun ;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun wdt_trgr_pattern = ~wdt_trgr_pattern;
61*4882a593Smuzhiyun writel(wdt_trgr_pattern, &wdt->wdtwtgr);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* wait for posted write to complete */
64*4882a593Smuzhiyun while ((readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WTGR))
65*4882a593Smuzhiyun ;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
omap_wdt_set_timeout(unsigned int timeout)68*4882a593Smuzhiyun static int omap_wdt_set_timeout(unsigned int timeout)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
71*4882a593Smuzhiyun u32 pre_margin = GET_WLDR_VAL(timeout);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* just count up at 32 KHz */
74*4882a593Smuzhiyun while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
75*4882a593Smuzhiyun ;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun writel(pre_margin, &wdt->wdtwldr);
78*4882a593Smuzhiyun while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR)
79*4882a593Smuzhiyun ;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
hw_watchdog_disable(void)84*4882a593Smuzhiyun void hw_watchdog_disable(void)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * Disable watchdog
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun writel(0xAAAA, &wdt->wdtwspr);
92*4882a593Smuzhiyun while (readl(&wdt->wdtwwps) != 0x0)
93*4882a593Smuzhiyun ;
94*4882a593Smuzhiyun writel(0x5555, &wdt->wdtwspr);
95*4882a593Smuzhiyun while (readl(&wdt->wdtwwps) != 0x0)
96*4882a593Smuzhiyun ;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
hw_watchdog_init(void)99*4882a593Smuzhiyun void hw_watchdog_init(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct wd_timer *wdt = (struct wd_timer *)WDT_BASE;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun * Make sure the watchdog is disabled. This is unfortunately required
105*4882a593Smuzhiyun * because writing to various registers with the watchdog running has no
106*4882a593Smuzhiyun * effect.
107*4882a593Smuzhiyun */
108*4882a593Smuzhiyun hw_watchdog_disable();
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* initialize prescaler */
111*4882a593Smuzhiyun while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
112*4882a593Smuzhiyun ;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun writel(WDT_WCLR_PRE | (PTV << WDT_WCLR_PTV_OFF), &wdt->wdtwclr);
115*4882a593Smuzhiyun while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR)
116*4882a593Smuzhiyun ;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun omap_wdt_set_timeout(WDT_HW_TIMEOUT);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Sequence to enable the watchdog */
121*4882a593Smuzhiyun writel(0xBBBB, &wdt->wdtwspr);
122*4882a593Smuzhiyun while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
123*4882a593Smuzhiyun ;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun writel(0x4444, &wdt->wdtwspr);
126*4882a593Smuzhiyun while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
127*4882a593Smuzhiyun ;
128*4882a593Smuzhiyun }
129