1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * watchdog.c - driver for i.mx on-chip watchdog 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Licensed under the GPL-2 or later. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <watchdog.h> 10*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 11*4882a593Smuzhiyun #include <fsl_wdog.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_IMX_WATCHDOG hw_watchdog_reset(void)14*4882a593Smuzhiyunvoid hw_watchdog_reset(void) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun writew(0x5555, &wdog->wsr); 19*4882a593Smuzhiyun writew(0xaaaa, &wdog->wsr); 20*4882a593Smuzhiyun } 21*4882a593Smuzhiyun hw_watchdog_init(void)22*4882a593Smuzhiyunvoid hw_watchdog_init(void) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 25*4882a593Smuzhiyun u16 timeout; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * The timer watchdog can be set between 29*4882a593Smuzhiyun * 0.5 and 128 Seconds. If not defined 30*4882a593Smuzhiyun * in configuration file, sets 128 Seconds 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS 33*4882a593Smuzhiyun #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; 36*4882a593Smuzhiyun writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | 37*4882a593Smuzhiyun WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); 38*4882a593Smuzhiyun hw_watchdog_reset(); 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun reset_cpu(ulong addr)42*4882a593Smuzhiyunvoid __attribute__((weak)) reset_cpu(ulong addr) 43*4882a593Smuzhiyun { 44*4882a593Smuzhiyun struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun writew(0x5555, &wdog->wsr); 49*4882a593Smuzhiyun writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ 50*4882a593Smuzhiyun while (1) { 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * spin for .5 seconds before reset 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun } 56