1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c] 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Watchdog driver for Atmel AT91SAM9x processors. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 7*4882a593Smuzhiyun * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * The Watchdog Timer Mode Register can be only written to once. If the 14*4882a593Smuzhiyun * timeout need to be set from U-Boot, be sure that the bootstrap doesn't 15*4882a593Smuzhiyun * write to this register. Inform Linux to it too 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <common.h> 19*4882a593Smuzhiyun #include <watchdog.h> 20*4882a593Smuzhiyun #include <asm/arch/hardware.h> 21*4882a593Smuzhiyun #include <asm/io.h> 22*4882a593Smuzhiyun #include <asm/arch/at91_wdt.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, 26*4882a593Smuzhiyun * use this to convert a watchdog 27*4882a593Smuzhiyun * value from/to milliseconds. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define ms_to_ticks(t) (((t << 8) / 1000) - 1) 30*4882a593Smuzhiyun #define ticks_to_ms(t) (((t + 1) * 1000) >> 8) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Hardware timeout in seconds */ 33*4882a593Smuzhiyun #if !defined(CONFIG_AT91_HW_WDT_TIMEOUT) 34*4882a593Smuzhiyun #define WDT_HW_TIMEOUT 2 35*4882a593Smuzhiyun #else 36*4882a593Smuzhiyun #define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * Set the watchdog time interval in 1/256Hz (write-once) 41*4882a593Smuzhiyun * Counter is 12 bit. 42*4882a593Smuzhiyun */ at91_wdt_settimeout(unsigned int timeout)43*4882a593Smuzhiyunstatic int at91_wdt_settimeout(unsigned int timeout) 44*4882a593Smuzhiyun { 45*4882a593Smuzhiyun unsigned int reg; 46*4882a593Smuzhiyun at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Check if disabled */ 49*4882a593Smuzhiyun if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) { 50*4882a593Smuzhiyun printf("sorry, watchdog is disabled\n"); 51*4882a593Smuzhiyun return -1; 52*4882a593Smuzhiyun } 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * All counting occurs at SLOW_CLOCK / 128 = 256 Hz 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun * Since WDV is a 12-bit counter, the maximum period is 58*4882a593Smuzhiyun * 4096 / 256 = 16 seconds. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */ 62*4882a593Smuzhiyun | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */ 63*4882a593Smuzhiyun | AT91_WDT_MR_WDD(0xfff) /* restart at any time */ 64*4882a593Smuzhiyun | AT91_WDT_MR_WDV(timeout); /* timer value */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun writel(reg, &wd->mr); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun return 0; 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun hw_watchdog_reset(void)71*4882a593Smuzhiyunvoid hw_watchdog_reset(void) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT; 74*4882a593Smuzhiyun writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr); 75*4882a593Smuzhiyun } 76*4882a593Smuzhiyun hw_watchdog_init(void)77*4882a593Smuzhiyunvoid hw_watchdog_init(void) 78*4882a593Smuzhiyun { 79*4882a593Smuzhiyun /* 16 seconds timer, resets enabled */ 80*4882a593Smuzhiyun at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000)); 81*4882a593Smuzhiyun } 82