1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <clk.h>
9*4882a593Smuzhiyun #include <display.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <dw_hdmi.h>
12*4882a593Smuzhiyun #include <edid.h>
13*4882a593Smuzhiyun #include <regmap.h>
14*4882a593Smuzhiyun #include <syscon.h>
15*4882a593Smuzhiyun #include <asm/gpio.h>
16*4882a593Smuzhiyun #include <asm/io.h>
17*4882a593Smuzhiyun #include <asm/arch/clock.h>
18*4882a593Smuzhiyun #include <asm/arch/hardware.h>
19*4882a593Smuzhiyun #include <asm/arch/grf_rk3399.h>
20*4882a593Smuzhiyun #include <power/regulator.h>
21*4882a593Smuzhiyun #include "rk_hdmi.h"
22*4882a593Smuzhiyun
rk3399_hdmi_enable(struct udevice * dev,int panel_bpp,const struct display_timing * edid)23*4882a593Smuzhiyun static int rk3399_hdmi_enable(struct udevice *dev, int panel_bpp,
24*4882a593Smuzhiyun const struct display_timing *edid)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun struct rk_hdmi_priv *priv = dev_get_priv(dev);
27*4882a593Smuzhiyun struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
28*4882a593Smuzhiyun int vop_id = uc_plat->source_id;
29*4882a593Smuzhiyun struct rk3399_grf_regs *grf = priv->grf;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* select the hdmi encoder input data from our source_id */
32*4882a593Smuzhiyun rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK,
33*4882a593Smuzhiyun (vop_id == 1) ? GRF_RK3399_HDMI_VOP_SEL_L : 0);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return dw_hdmi_enable(&priv->hdmi, edid);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
rk3399_hdmi_ofdata_to_platdata(struct udevice * dev)38*4882a593Smuzhiyun static int rk3399_hdmi_ofdata_to_platdata(struct udevice *dev)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun struct rk_hdmi_priv *priv = dev_get_priv(dev);
41*4882a593Smuzhiyun struct dw_hdmi *hdmi = &priv->hdmi;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun hdmi->i2c_clk_high = 0x7a;
44*4882a593Smuzhiyun hdmi->i2c_clk_low = 0x8d;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return rk_hdmi_ofdata_to_platdata(dev);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const char * const rk3399_regulator_names[] = {
50*4882a593Smuzhiyun "vcc1v8_hdmi",
51*4882a593Smuzhiyun "vcc0v9_hdmi"
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
rk3399_hdmi_probe(struct udevice * dev)54*4882a593Smuzhiyun static int rk3399_hdmi_probe(struct udevice *dev)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun /* Enable regulators required for HDMI */
57*4882a593Smuzhiyun rk_hdmi_probe_regulators(dev, rk3399_regulator_names,
58*4882a593Smuzhiyun ARRAY_SIZE(rk3399_regulator_names));
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun return rk_hdmi_probe(dev);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun static const struct dm_display_ops rk3399_hdmi_ops = {
64*4882a593Smuzhiyun .read_edid = rk_hdmi_read_edid,
65*4882a593Smuzhiyun .enable = rk3399_hdmi_enable,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static const struct udevice_id rk3399_hdmi_ids[] = {
69*4882a593Smuzhiyun { .compatible = "rockchip,rk3399-dw-hdmi" },
70*4882a593Smuzhiyun { }
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun U_BOOT_DRIVER(rk3399_hdmi_rockchip) = {
74*4882a593Smuzhiyun .name = "rk3399_hdmi_rockchip",
75*4882a593Smuzhiyun .id = UCLASS_DISPLAY,
76*4882a593Smuzhiyun .of_match = rk3399_hdmi_ids,
77*4882a593Smuzhiyun .ops = &rk3399_hdmi_ops,
78*4882a593Smuzhiyun .ofdata_to_platdata = rk3399_hdmi_ofdata_to_platdata,
79*4882a593Smuzhiyun .probe = rk3399_hdmi_probe,
80*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
81*4882a593Smuzhiyun };
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