xref: /OK3568_Linux_fs/u-boot/drivers/video/rk_eink/tps65185.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:     GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <asm/gpio.h>
11*4882a593Smuzhiyun #include "rk_ebc.h"
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define msleep(a)		udelay((a) * 1000)
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun struct tps65185_priv_data {
16*4882a593Smuzhiyun 	struct udevice *dev;
17*4882a593Smuzhiyun 	struct gpio_desc pwr_up_gpio;
18*4882a593Smuzhiyun 	struct gpio_desc pwr_en_gpio;
19*4882a593Smuzhiyun 	struct gpio_desc vcom_gpio;
20*4882a593Smuzhiyun 	struct gpio_desc wake_up_gpio;
21*4882a593Smuzhiyun 	u8 rev_id;
22*4882a593Smuzhiyun 	u8 vadj;
23*4882a593Smuzhiyun 	u8 vcom1;
24*4882a593Smuzhiyun 	u8 vcom2;
25*4882a593Smuzhiyun 	u8 upseq0;
26*4882a593Smuzhiyun 	u8 upseq1;
27*4882a593Smuzhiyun 	u8 dwnseq0;
28*4882a593Smuzhiyun 	u8 dwnseq1;
29*4882a593Smuzhiyun 	u8 shadow_en;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define REG_TMST_VALUE		0x00
33*4882a593Smuzhiyun #define REG_ENABLE		0x01
34*4882a593Smuzhiyun #define REG_VADJ		0x02
35*4882a593Smuzhiyun #define REG_VCOM1_ADJUST	0x03
36*4882a593Smuzhiyun #define REG_VCOM2_ADJUST	0x04
37*4882a593Smuzhiyun #define REG_INT_ENABLE1		0x05
38*4882a593Smuzhiyun #define REG_INT_ENABLE2		0x06
39*4882a593Smuzhiyun #define REG_INT_STATUS1		0x07
40*4882a593Smuzhiyun #define REG_INT_STATUS2		0x08
41*4882a593Smuzhiyun #define REG_UPSEQ0		0x09
42*4882a593Smuzhiyun #define REG_UPSEQ1		0x0a
43*4882a593Smuzhiyun #define REG_DWNSEQ0		0x0b
44*4882a593Smuzhiyun #define REG_DWNSEQ1		0x0c
45*4882a593Smuzhiyun #define REG_TMST1		0x0d
46*4882a593Smuzhiyun #define REG_TMST2		0x0e
47*4882a593Smuzhiyun #define REG_PG_STATUS		0x0f
48*4882a593Smuzhiyun #define REG_REVID		0x10
49*4882a593Smuzhiyun #define mv_to_vcom1_reg(mv)	(((mv) / 10) & 0xff)
50*4882a593Smuzhiyun #define mv_to_vcom2_reg(mv)	((((mv) / 10) & 0x100) >> 8)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun  * After waking up from sleep, Papyrus
54*4882a593Smuzhiyun  * waits for VN to be discharged and all
55*4882a593Smuzhiyun  * voltage ref to startup before loading
56*4882a593Smuzhiyun  * the default EEPROM settings. So accessing
57*4882a593Smuzhiyun  * registers too early after WAKEUP could
58*4882a593Smuzhiyun  * cause the register to be overridden by
59*4882a593Smuzhiyun  * default values
60*4882a593Smuzhiyun  */
61*4882a593Smuzhiyun #define PAPYRUS_EEPROM_DELAY_MS 50
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun  * Papyrus WAKEUP pin must stay low for
64*4882a593Smuzhiyun  * a minimum time
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun #define PAPYRUS_SLEEP_MINIMUM_MS 110
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun  * Temp sensor might take a little time to
69*4882a593Smuzhiyun  * settle even though the status bit in TMST1
70*4882a593Smuzhiyun  * state conversion is done - if read too early
71*4882a593Smuzhiyun  * 0C will be returned instead of the right temp
72*4882a593Smuzhiyun  */
73*4882a593Smuzhiyun #define PAPYRUS_TEMP_READ_TIME_MS 10
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun  * Powerup sequence takes at least 24 ms
77*4882a593Smuzhiyun  * - no need to poll too frequently
78*4882a593Smuzhiyun  */
79*4882a593Smuzhiyun #define HW_GET_STATE_INTERVAL_MS 24
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define SEQ_VDD(index)	(((index) % 4) << 6)
82*4882a593Smuzhiyun #define SEQ_VPOS(index)	(((index) % 4) << 4)
83*4882a593Smuzhiyun #define SEQ_VEE(index)	(((index) % 4) << 2)
84*4882a593Smuzhiyun #define SEQ_VNEG(index)	(((index) % 4) << 0)
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /* power up seq delay time */
87*4882a593Smuzhiyun #define UDLY_3ms(index)		(0x00 << (((index) % 4) * 2))
88*4882a593Smuzhiyun #define UDLY_6ms(index)		(0x01 << (((index) % 4) * 2))
89*4882a593Smuzhiyun #define UDLY_9ms(index)		(0x10 << (((index) % 4) * 2))
90*4882a593Smuzhiyun #define UDLY_12ms(index)	(0x11 << (((index) % 4) * 2))
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /* power down seq delay time */
93*4882a593Smuzhiyun #define DDLY_6ms(index)		(0x00 << (((index) % 4) * 2))
94*4882a593Smuzhiyun #define DDLY_12ms(index)	(0x01 << (((index) % 4) * 2))
95*4882a593Smuzhiyun #define DDLY_24ms(index)	(0x10 << (((index) % 4) * 2))
96*4882a593Smuzhiyun #define DDLY_48ms(index)	(0x11 << (((index) % 4) * 2))
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define NUMBER_PMIC_REGS		10
99*4882a593Smuzhiyun // INT_ENABLE1
100*4882a593Smuzhiyun #define PAPYRUS_INT_ENABLE1_ACQC_EN	1
101*4882a593Smuzhiyun #define PAPYRUS_INT_ENABLE1_PRGC_EN	0
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun // INT_STATUS1
104*4882a593Smuzhiyun #define PAPYRUS_INT_STATUS1_ACQC	1
105*4882a593Smuzhiyun #define PAPYRUS_INT_STATUS1_PRGC	0
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun // VCOM2_ADJUST
108*4882a593Smuzhiyun #define PAPYRUS_VCOM2_ACQ		7
109*4882a593Smuzhiyun #define PAPYRUS_VCOM2_PROG		6
110*4882a593Smuzhiyun #define PAPYRUS_VCOM2_HIZ		5
111*4882a593Smuzhiyun #define V3P3_EN_MASK			0x20
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun #define PAPYRUS_V3P3OFF_DELAY_MS	20//100
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static struct udevice *pmic_dev;
116*4882a593Smuzhiyun 
tps65185_i2c_write(struct tps65185_priv_data * priv_data,u8 reg,u8 val)117*4882a593Smuzhiyun int tps65185_i2c_write(struct tps65185_priv_data *priv_data, u8 reg, u8 val)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	int ret;
120*4882a593Smuzhiyun 	u8 buf[2];
121*4882a593Smuzhiyun 	struct i2c_msg msg;
122*4882a593Smuzhiyun 	struct dm_i2c_chip *chip = dev_get_parent_platdata(priv_data->dev);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	buf[0] = reg;
125*4882a593Smuzhiyun 	buf[1] = val;
126*4882a593Smuzhiyun 	msg.addr = chip->chip_addr;
127*4882a593Smuzhiyun 	msg.flags = 0;
128*4882a593Smuzhiyun 	msg.len = 2;
129*4882a593Smuzhiyun 	msg.buf = buf;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	ret = dm_i2c_xfer(priv_data->dev, &msg, 1);
132*4882a593Smuzhiyun 	if (ret) {
133*4882a593Smuzhiyun 		printf("tps65185 i2c write failed: %d\n", ret);
134*4882a593Smuzhiyun 		return ret;
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
tps65185_i2c_read(struct tps65185_priv_data * priv_data,u8 reg,u8 * val)140*4882a593Smuzhiyun int tps65185_i2c_read(struct tps65185_priv_data *priv_data, u8 reg, u8 *val)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	int ret;
143*4882a593Smuzhiyun 	u8 data;
144*4882a593Smuzhiyun 	struct dm_i2c_chip *chip = dev_get_parent_platdata(priv_data->dev);
145*4882a593Smuzhiyun 	struct i2c_msg msg[] = {
146*4882a593Smuzhiyun 		{
147*4882a593Smuzhiyun 			.addr = chip->chip_addr,
148*4882a593Smuzhiyun 			.flags = 0,
149*4882a593Smuzhiyun 			.buf = (u8 *)&reg,
150*4882a593Smuzhiyun 			.len = 1,
151*4882a593Smuzhiyun 		}, {
152*4882a593Smuzhiyun 			.addr = chip->chip_addr,
153*4882a593Smuzhiyun 			.flags = I2C_M_RD,
154*4882a593Smuzhiyun 			.buf = (u8 *)&data,
155*4882a593Smuzhiyun 			.len = 1,
156*4882a593Smuzhiyun 		}
157*4882a593Smuzhiyun 	};
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	ret = dm_i2c_xfer(priv_data->dev, msg, 2);
160*4882a593Smuzhiyun 	if (ret) {
161*4882a593Smuzhiyun 		printf("tps65185 i2c read failed: %d\n", ret);
162*4882a593Smuzhiyun 		return ret;
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	*val = data;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	return 0;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
tps65185_dump_registers(void)170*4882a593Smuzhiyun void tps65185_dump_registers(void)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	u8 i, reg = 0;
173*4882a593Smuzhiyun 	struct tps65185_priv_data *priv_data = dev_get_priv(pmic_dev);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	for (i = 0; i <= REG_REVID; i++) {
176*4882a593Smuzhiyun 		tps65185_i2c_read(priv_data, i, &reg);
177*4882a593Smuzhiyun 		printf("0x%x\t", reg);
178*4882a593Smuzhiyun 	}
179*4882a593Smuzhiyun 	printf("\n");
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
tps65185_read_vcom_value(struct tps65185_priv_data * priv_data,u32 * vcom_read)182*4882a593Smuzhiyun static int tps65185_read_vcom_value(struct tps65185_priv_data *priv_data,
183*4882a593Smuzhiyun 				    u32 *vcom_read)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun 	int ret;
186*4882a593Smuzhiyun 	u8 vcom_reg;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	dm_gpio_set_value(&priv_data->wake_up_gpio, 0);
189*4882a593Smuzhiyun 	msleep(10);
190*4882a593Smuzhiyun 	dm_gpio_set_value(&priv_data->wake_up_gpio, 1);
191*4882a593Smuzhiyun 	msleep(10);
192*4882a593Smuzhiyun 	ret = tps65185_i2c_read(priv_data, REG_VCOM1_ADJUST, &vcom_reg);
193*4882a593Smuzhiyun 	if (ret) {
194*4882a593Smuzhiyun 		printf("read vcom failed: %d\n", ret);
195*4882a593Smuzhiyun 		return ret;
196*4882a593Smuzhiyun 	}
197*4882a593Smuzhiyun 	*vcom_read = vcom_reg;
198*4882a593Smuzhiyun 	ret = tps65185_i2c_read(priv_data, REG_VCOM2_ADJUST, &vcom_reg);
199*4882a593Smuzhiyun 	if (ret) {
200*4882a593Smuzhiyun 		printf("read vcom failed: %d\n", ret);
201*4882a593Smuzhiyun 		return ret;
202*4882a593Smuzhiyun 	}
203*4882a593Smuzhiyun 	*vcom_read += (vcom_reg & 0x1) << 8;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	printf("read vcom value: %d\n", *vcom_read);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	return 0;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
tps65185_set_vcom_value(struct udevice * dev,u32 set_value)210*4882a593Smuzhiyun static int tps65185_set_vcom_value(struct udevice *dev, u32 set_value)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun 	int ret = 0;
213*4882a593Smuzhiyun 	u32 vcom_readback = 0;
214*4882a593Smuzhiyun 	u8 vcom1_val, vcom2_val, int_stat = 0;
215*4882a593Smuzhiyun 	struct tps65185_priv_data *priv_data = dev_get_priv(dev);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	ret = tps65185_read_vcom_value(priv_data, &vcom_readback);
218*4882a593Smuzhiyun 	if (ret < 0) {
219*4882a593Smuzhiyun 		printf("tps65185 read vcom value failed\n");
220*4882a593Smuzhiyun 	} else {
221*4882a593Smuzhiyun 		if (vcom_readback == set_value / 10) {
222*4882a593Smuzhiyun 			printf("Same as pmic default value, just return.\n");
223*4882a593Smuzhiyun 			return 0;
224*4882a593Smuzhiyun 		}
225*4882a593Smuzhiyun 	}
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	vcom1_val = mv_to_vcom1_reg(set_value);
228*4882a593Smuzhiyun 	vcom2_val = mv_to_vcom2_reg(set_value);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	dm_gpio_set_value(&priv_data->wake_up_gpio, 1);
231*4882a593Smuzhiyun 	msleep(20);
232*4882a593Smuzhiyun 	// Set vcom voltage
233*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_VCOM1_ADJUST, vcom1_val);
234*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_VCOM2_ADJUST, vcom2_val);
235*4882a593Smuzhiyun 	// PROGRAMMING
236*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_VCOM2_ADJUST,
237*4882a593Smuzhiyun 			   vcom2_val | (1 << PAPYRUS_VCOM2_PROG));
238*4882a593Smuzhiyun 	do {
239*4882a593Smuzhiyun 		msleep(20);
240*4882a593Smuzhiyun 		ret = tps65185_i2c_read(priv_data, REG_INT_STATUS1, &int_stat);
241*4882a593Smuzhiyun 		if (ret) {
242*4882a593Smuzhiyun 			printf("read status1 failed: %d\n", ret);
243*4882a593Smuzhiyun 			break;
244*4882a593Smuzhiyun 		}
245*4882a593Smuzhiyun 	} while (!(int_stat & (1 << PAPYRUS_INT_STATUS1_PRGC)));
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	// VERIFICATION
248*4882a593Smuzhiyun 	tps65185_read_vcom_value(priv_data, &vcom_readback);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	if (vcom_readback != set_value / 10) {
251*4882a593Smuzhiyun 		printf("vcom set failed, expect: %d, readback: %d\n",
252*4882a593Smuzhiyun 		       set_value, vcom_readback);
253*4882a593Smuzhiyun 		return -1;
254*4882a593Smuzhiyun 	}
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	return 0;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun 
tps65185_hw_power_ack(struct tps65185_priv_data * priv_data,int up)259*4882a593Smuzhiyun static bool tps65185_hw_power_ack(struct tps65185_priv_data *priv_data, int up)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	u8 pg_status;
262*4882a593Smuzhiyun 	int st, ret, retries_left = 10;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	do {
265*4882a593Smuzhiyun 		ret = tps65185_i2c_read(priv_data, REG_PG_STATUS, &pg_status);
266*4882a593Smuzhiyun 		if (ret)
267*4882a593Smuzhiyun 			printf("read REG_PG_STATUS failed: %d\n", ret);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 		pg_status &= 0xfa;
270*4882a593Smuzhiyun 		if (pg_status == 0xfa && up == 1) {
271*4882a593Smuzhiyun 			st = 1;
272*4882a593Smuzhiyun 		} else if (pg_status == 0x00 && up == 0) {
273*4882a593Smuzhiyun 			st = 0;
274*4882a593Smuzhiyun 		} else {
275*4882a593Smuzhiyun 			st = -1;	/* not settled yet */
276*4882a593Smuzhiyun 			msleep(HW_GET_STATE_INTERVAL_MS);
277*4882a593Smuzhiyun 		}
278*4882a593Smuzhiyun 		retries_left--;
279*4882a593Smuzhiyun 	} while ((st == -1) && retries_left);
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 	if ((st == -1) && !retries_left)
282*4882a593Smuzhiyun 		printf("power %s settle error (PG = %02x)\n",
283*4882a593Smuzhiyun 		       up ? "up" : "down", pg_status);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	return (st == up);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun 
tps65185_power_on(struct udevice * dev)288*4882a593Smuzhiyun static int tps65185_power_on(struct udevice *dev)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun 	struct tps65185_priv_data *priv_data = dev_get_priv(dev);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_VADJ, priv_data->vadj);
293*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_UPSEQ0, priv_data->upseq0);
294*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_UPSEQ1, priv_data->upseq1);
295*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_DWNSEQ0, priv_data->dwnseq0);
296*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_DWNSEQ1, priv_data->dwnseq1);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	priv_data->shadow_en |= V3P3_EN_MASK;
299*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_ENABLE, priv_data->shadow_en);
300*4882a593Smuzhiyun 	msleep(PAPYRUS_V3P3OFF_DELAY_MS);
301*4882a593Smuzhiyun 	priv_data->shadow_en = (0x80 | 0x30 | 0x0F);
302*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_ENABLE, priv_data->shadow_en);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	tps65185_hw_power_ack(priv_data, 1);
305*4882a593Smuzhiyun 	return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun 
tps65185_power_down(struct udevice * dev)308*4882a593Smuzhiyun static int tps65185_power_down(struct udevice *dev)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	struct tps65185_priv_data *priv_data = dev_get_priv(dev);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	priv_data->shadow_en = (0x40 | 0x20 | 0x0F);
313*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_ENABLE, priv_data->shadow_en);
314*4882a593Smuzhiyun 	msleep(PAPYRUS_V3P3OFF_DELAY_MS);
315*4882a593Smuzhiyun 	priv_data->shadow_en &= ~V3P3_EN_MASK;
316*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_ENABLE, priv_data->shadow_en);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	tps65185_hw_power_ack(priv_data, 0);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun 
tps65185_temp_get(struct udevice * dev,u32 * temp)323*4882a593Smuzhiyun static int tps65185_temp_get(struct udevice *dev, u32 *temp)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun 	int ret;
326*4882a593Smuzhiyun 	u8 read_val = 0;
327*4882a593Smuzhiyun 	struct tps65185_priv_data *priv_data = dev_get_priv(dev);
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_TMST1, 0x80);
330*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_TMST1, 0x80);
331*4882a593Smuzhiyun 	do {
332*4882a593Smuzhiyun 		int retry_time = 100;
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 		ret = tps65185_i2c_read(priv_data, REG_TMST1, &read_val);
335*4882a593Smuzhiyun 		if (ret < 0) {
336*4882a593Smuzhiyun 			printf("read REG_TMST1 failed: %d\n", ret);
337*4882a593Smuzhiyun 			return ret;
338*4882a593Smuzhiyun 		}
339*4882a593Smuzhiyun 		if (retry_time-- == 0) {
340*4882a593Smuzhiyun 			printf("read REG_TMST1 retry 100 times\n");
341*4882a593Smuzhiyun 			break;
342*4882a593Smuzhiyun 		}
343*4882a593Smuzhiyun 		debug("read_val = 0x%x\n", read_val);
344*4882a593Smuzhiyun 	} while (((read_val & 0x20) == 0 || (read_val & 0x80)));
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	mdelay(PAPYRUS_TEMP_READ_TIME_MS);
347*4882a593Smuzhiyun 	ret = tps65185_i2c_read(priv_data, REG_TMST_VALUE, &read_val);
348*4882a593Smuzhiyun 	if (ret) {
349*4882a593Smuzhiyun 		printf("read REG_TMST_VALUE failed: %d\n", ret);
350*4882a593Smuzhiyun 		return ret;
351*4882a593Smuzhiyun 	}
352*4882a593Smuzhiyun 	*temp = (u32)read_val;
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	return 0;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
tps65185_hw_init(struct udevice * dev)357*4882a593Smuzhiyun static int tps65185_hw_init(struct udevice *dev)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun 	int ret;
360*4882a593Smuzhiyun 	u8 rev_id = 0;
361*4882a593Smuzhiyun 	struct tps65185_priv_data *priv_data = dev_get_priv(dev);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	dm_gpio_set_value(&priv_data->wake_up_gpio, 0);
364*4882a593Smuzhiyun 	mdelay(PAPYRUS_SLEEP_MINIMUM_MS);
365*4882a593Smuzhiyun 	dm_gpio_set_value(&priv_data->wake_up_gpio, 1);
366*4882a593Smuzhiyun 	dm_gpio_set_value(&priv_data->pwr_up_gpio, 0);
367*4882a593Smuzhiyun 	dm_gpio_set_value(&priv_data->vcom_gpio, 1);
368*4882a593Smuzhiyun 	mdelay(PAPYRUS_EEPROM_DELAY_MS);
369*4882a593Smuzhiyun 	ret = tps65185_i2c_read(priv_data, REG_REVID, &rev_id);
370*4882a593Smuzhiyun 	if (ret) {
371*4882a593Smuzhiyun 		printf("read revid failed: %d\n", ret);
372*4882a593Smuzhiyun 		return ret;
373*4882a593Smuzhiyun 	}
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	if (rev_id > 0)
376*4882a593Smuzhiyun 		printf("detected device with ID=%02x (TPS6518%dr%dp%d)\n",
377*4882a593Smuzhiyun 		       rev_id, rev_id & 0xF, (rev_id & 0xC0) >> 6,
378*4882a593Smuzhiyun 		       (rev_id & 0x30) >> 4);
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	tps65185_i2c_write(priv_data, REG_ENABLE, priv_data->shadow_en);
381*4882a593Smuzhiyun 	priv_data->rev_id = rev_id;
382*4882a593Smuzhiyun 	printf("rev_id=%x\n", rev_id);
383*4882a593Smuzhiyun 	return 0;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun 
tps65185_init_arg(struct tps65185_priv_data * priv_data)386*4882a593Smuzhiyun static void tps65185_init_arg(struct tps65185_priv_data *priv_data)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun 	priv_data->vadj = 0x03;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	priv_data->upseq0 = SEQ_VEE(0) | SEQ_VNEG(1)
391*4882a593Smuzhiyun 				| SEQ_VPOS(2) | SEQ_VDD(3);
392*4882a593Smuzhiyun 	priv_data->upseq1 = UDLY_3ms(0) | UDLY_3ms(1)
393*4882a593Smuzhiyun 				| UDLY_3ms(2) | UDLY_3ms(3);
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	priv_data->dwnseq0 = SEQ_VDD(0) | SEQ_VPOS(1)
396*4882a593Smuzhiyun 				| SEQ_VNEG(2) | SEQ_VEE(3);
397*4882a593Smuzhiyun 	priv_data->dwnseq1 = DDLY_6ms(0) | DDLY_6ms(1)
398*4882a593Smuzhiyun 				| DDLY_6ms(2) | DDLY_6ms(3);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	priv_data->vcom1 = mv_to_vcom1_reg(1560);
401*4882a593Smuzhiyun 	priv_data->vcom2 = mv_to_vcom2_reg(1560);
402*4882a593Smuzhiyun 	priv_data->shadow_en = 0;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun 
tps65185_probe(struct udevice * dev)405*4882a593Smuzhiyun static int tps65185_probe(struct udevice *dev)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun 	int ret;
408*4882a593Smuzhiyun 	struct tps65185_priv_data *tps65185_priv = dev_get_priv(dev);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	tps65185_priv->dev = dev;
411*4882a593Smuzhiyun 	pmic_dev = dev;
412*4882a593Smuzhiyun 	tps65185_init_arg(tps65185_priv);
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	ret = gpio_request_by_name(dev, "wakeup-gpios", 0,
415*4882a593Smuzhiyun 				   &tps65185_priv->wake_up_gpio, GPIOD_IS_OUT);
416*4882a593Smuzhiyun 	if (ret) {
417*4882a593Smuzhiyun 		printf("Cannot get wakeup_pin GPIO: %d\n", ret);
418*4882a593Smuzhiyun 		return ret;
419*4882a593Smuzhiyun 	}
420*4882a593Smuzhiyun 	ret = gpio_request_by_name(dev, "powerup-gpios", 0,
421*4882a593Smuzhiyun 				   &tps65185_priv->pwr_up_gpio, GPIOD_IS_OUT);
422*4882a593Smuzhiyun 	if (ret) {
423*4882a593Smuzhiyun 		printf("Cannot get pwr_up_gpio GPIO: %d\n", ret);
424*4882a593Smuzhiyun 		return ret;
425*4882a593Smuzhiyun 	}
426*4882a593Smuzhiyun 	ret = gpio_request_by_name(dev, "vcomctl-gpios", 0,
427*4882a593Smuzhiyun 				   &tps65185_priv->vcom_gpio, GPIOD_IS_OUT);
428*4882a593Smuzhiyun 	if (ret) {
429*4882a593Smuzhiyun 		printf("Cannot get vcom_gpio GPIO: %d\n", ret);
430*4882a593Smuzhiyun 		return ret;
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 	ret = gpio_request_by_name(dev, "poweren-gpios", 0,
433*4882a593Smuzhiyun 				   &tps65185_priv->pwr_en_gpio, GPIOD_IS_OUT);
434*4882a593Smuzhiyun 	if (!ret)
435*4882a593Smuzhiyun 		dm_gpio_set_value(&tps65185_priv->pwr_en_gpio, 1);
436*4882a593Smuzhiyun 	else
437*4882a593Smuzhiyun 		printf("Cannot get pwren_pin GPIO: %d\n", ret);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	ret = tps65185_hw_init(dev);
440*4882a593Smuzhiyun 	if (ret) {
441*4882a593Smuzhiyun 		printf("Cannot init hardware for tps65185: %d\n", ret);
442*4882a593Smuzhiyun 		return ret;
443*4882a593Smuzhiyun 	}
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	return 0;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun const struct rk_ebc_pwr_ops tps65185_funcs = {
449*4882a593Smuzhiyun 	.power_on = tps65185_power_on,
450*4882a593Smuzhiyun 	.power_down = tps65185_power_down,
451*4882a593Smuzhiyun 	.temp_get = tps65185_temp_get,
452*4882a593Smuzhiyun 	.vcom_set = tps65185_set_vcom_value,
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static const struct udevice_id ebc_power_of_match[] = {
456*4882a593Smuzhiyun 	{ .compatible = "ti,tps65185" },
457*4882a593Smuzhiyun 	{}
458*4882a593Smuzhiyun };
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun U_BOOT_DRIVER(tps65185_ebc_pwr) = {
461*4882a593Smuzhiyun 	.name = "tps65185_ebc_pwr",
462*4882a593Smuzhiyun 	.id = UCLASS_I2C_GENERIC,
463*4882a593Smuzhiyun 	.of_match = ebc_power_of_match,
464*4882a593Smuzhiyun 	.probe = tps65185_probe,
465*4882a593Smuzhiyun 	.ops = &tps65185_funcs,
466*4882a593Smuzhiyun 	.bind = dm_scan_fdt_dev,
467*4882a593Smuzhiyun 	.priv_auto_alloc_size = sizeof(struct tps65185_priv_data),
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun 
470