1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun * Author: Wenping Zhang <wenping.zhang@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef RK_EBC_H 9*4882a593Smuzhiyun #define RK_EBC_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "epdlut/epd_lut.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct ebc_panel { 14*4882a593Smuzhiyun u32 width; 15*4882a593Smuzhiyun u32 height; 16*4882a593Smuzhiyun u32 vir_width; 17*4882a593Smuzhiyun u32 vir_height; 18*4882a593Smuzhiyun u32 width_mm; 19*4882a593Smuzhiyun u32 height_mm; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun u32 sdck; 22*4882a593Smuzhiyun u32 lsl; 23*4882a593Smuzhiyun u32 lbl; 24*4882a593Smuzhiyun u32 ldl; 25*4882a593Smuzhiyun u32 lel; 26*4882a593Smuzhiyun u32 gdck_sta; 27*4882a593Smuzhiyun u32 lgonl; 28*4882a593Smuzhiyun u32 fsl; 29*4882a593Smuzhiyun u32 fbl; 30*4882a593Smuzhiyun u32 fdl; 31*4882a593Smuzhiyun u32 fel; 32*4882a593Smuzhiyun u32 panel_16bit; 33*4882a593Smuzhiyun u32 panel_color; 34*4882a593Smuzhiyun u32 mirror; 35*4882a593Smuzhiyun u32 rearrange; 36*4882a593Smuzhiyun u32 disp_pbuf; 37*4882a593Smuzhiyun u32 disp_pbuf_size; 38*4882a593Smuzhiyun u32 *lut_pbuf; 39*4882a593Smuzhiyun u32 lut_pbuf_size; 40*4882a593Smuzhiyun struct epd_lut_data lut_data; 41*4882a593Smuzhiyun struct epd_lut_ops lut_ops; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun struct rk_ebc_tcon_ops { 45*4882a593Smuzhiyun int (*enable)(struct udevice *dev, struct ebc_panel *panel); 46*4882a593Smuzhiyun int (*disable)(struct udevice *dev); 47*4882a593Smuzhiyun int (*dsp_mode_set)(struct udevice *dev, int update_mode, 48*4882a593Smuzhiyun int display_mode, int three_win_mode, 49*4882a593Smuzhiyun int eink_mode); 50*4882a593Smuzhiyun int (*image_addr_set)(struct udevice *dev, u32 pre_image_addr, 51*4882a593Smuzhiyun u32 cur_image_addr); 52*4882a593Smuzhiyun int (*frame_addr_set)(struct udevice *dev, u32 frame_addr); 53*4882a593Smuzhiyun int (*lut_data_set)(struct udevice *dev, unsigned int *lut_data, 54*4882a593Smuzhiyun int frame_count, int lut_32); 55*4882a593Smuzhiyun int (*frame_start)(struct udevice *dev, int frame_total); 56*4882a593Smuzhiyun int (*wait_for_last_frame_complete)(struct udevice *dev); 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define ebc_tcon_get_ops(dev) ((struct rk_ebc_tcon_ops *)(dev)->driver->ops) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun *interface for ebc power control 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun struct rk_ebc_pwr_ops { 65*4882a593Smuzhiyun int (*power_on)(struct udevice *dev); 66*4882a593Smuzhiyun int (*power_down)(struct udevice *dev); 67*4882a593Smuzhiyun int (*temp_get)(struct udevice *dev, u32 *temp); 68*4882a593Smuzhiyun int (*vcom_set)(struct udevice *dev, u32 vcom); 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define ebc_pwr_get_ops(dev) ((struct rk_ebc_pwr_ops *)(dev)->driver->ops) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun //display mode define 74*4882a593Smuzhiyun #define DIRECT_MODE 0 75*4882a593Smuzhiyun #define LUT_MODE 1 76*4882a593Smuzhiyun #define THREE_WIN_MODE 1 77*4882a593Smuzhiyun #define EINK_MODE 1 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif 80