1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Samsung Electronics 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: Donghwa Lee <dh09.lee@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _EXYNOS_EDP_LOWLEVEL_H 10*4882a593Smuzhiyun #define _EXYNOS_EDP_LOWLEVEL_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, 13*4882a593Smuzhiyun unsigned int enable); 14*4882a593Smuzhiyun void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, 15*4882a593Smuzhiyun unsigned int enable); 16*4882a593Smuzhiyun void exynos_dp_reset(struct exynos_dp *dp_regs); 17*4882a593Smuzhiyun void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable); 18*4882a593Smuzhiyun unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs, 19*4882a593Smuzhiyun unsigned int block, u32 enable); 20*4882a593Smuzhiyun unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs); 21*4882a593Smuzhiyun int exynos_dp_init_analog_func(struct exynos_dp *dp_regs); 22*4882a593Smuzhiyun void exynos_dp_init_hpd(struct exynos_dp *dp_regs); 23*4882a593Smuzhiyun void exynos_dp_init_aux(struct exynos_dp *dp_regs); 24*4882a593Smuzhiyun void exynos_dp_config_interrupt(struct exynos_dp *dp_regs); 25*4882a593Smuzhiyun unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs); 26*4882a593Smuzhiyun unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs); 27*4882a593Smuzhiyun unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs); 28*4882a593Smuzhiyun unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs, 29*4882a593Smuzhiyun unsigned int reg_addr, 30*4882a593Smuzhiyun unsigned char data); 31*4882a593Smuzhiyun unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs, 32*4882a593Smuzhiyun unsigned int reg_addr, 33*4882a593Smuzhiyun unsigned char *data); 34*4882a593Smuzhiyun unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs, 35*4882a593Smuzhiyun unsigned int reg_addr, 36*4882a593Smuzhiyun unsigned int count, 37*4882a593Smuzhiyun unsigned char data[]); 38*4882a593Smuzhiyun unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs, 39*4882a593Smuzhiyun unsigned int reg_addr, 40*4882a593Smuzhiyun unsigned int count, 41*4882a593Smuzhiyun unsigned char data[]); 42*4882a593Smuzhiyun int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs, 43*4882a593Smuzhiyun unsigned int device_addr, 44*4882a593Smuzhiyun unsigned int reg_addr); 45*4882a593Smuzhiyun int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs, 46*4882a593Smuzhiyun unsigned int device_addr, 47*4882a593Smuzhiyun unsigned int reg_addr, unsigned int *data); 48*4882a593Smuzhiyun int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs, 49*4882a593Smuzhiyun unsigned int device_addr, 50*4882a593Smuzhiyun unsigned int reg_addr, unsigned int count, 51*4882a593Smuzhiyun unsigned char edid[]); 52*4882a593Smuzhiyun void exynos_dp_reset_macro(struct exynos_dp *dp_regs); 53*4882a593Smuzhiyun void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs, 54*4882a593Smuzhiyun unsigned char bwtype); 55*4882a593Smuzhiyun unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs); 56*4882a593Smuzhiyun void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count); 57*4882a593Smuzhiyun unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs); 58*4882a593Smuzhiyun unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs, 59*4882a593Smuzhiyun unsigned char lanecnt); 60*4882a593Smuzhiyun void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs, 61*4882a593Smuzhiyun unsigned int level, unsigned char lanecnt); 62*4882a593Smuzhiyun void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs, 63*4882a593Smuzhiyun unsigned char request_val, 64*4882a593Smuzhiyun unsigned char lanecnt); 65*4882a593Smuzhiyun void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs, 66*4882a593Smuzhiyun unsigned int pattern); 67*4882a593Smuzhiyun void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs, 68*4882a593Smuzhiyun unsigned char enable); 69*4882a593Smuzhiyun void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, 70*4882a593Smuzhiyun unsigned int enable); 71*4882a593Smuzhiyun int exynos_dp_init_video(struct exynos_dp *dp_regs); 72*4882a593Smuzhiyun void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs, 73*4882a593Smuzhiyun struct edp_video_info *video_info); 74*4882a593Smuzhiyun void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs, 75*4882a593Smuzhiyun struct edp_video_info *video_info); 76*4882a593Smuzhiyun int exynos_dp_config_video_bist(struct exynos_dp *dp_regs, 77*4882a593Smuzhiyun struct exynos_dp_priv *priv); 78*4882a593Smuzhiyun unsigned int exynos_dp_is_slave_video_stream_clock_on( 79*4882a593Smuzhiyun struct exynos_dp *dp_regs); 80*4882a593Smuzhiyun void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type, 81*4882a593Smuzhiyun unsigned int m_value, unsigned int n_value); 82*4882a593Smuzhiyun void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs, 83*4882a593Smuzhiyun unsigned int type); 84*4882a593Smuzhiyun void exynos_dp_enable_video_master(struct exynos_dp *dp_regs, 85*4882a593Smuzhiyun unsigned int enable); 86*4882a593Smuzhiyun void exynos_dp_start_video(struct exynos_dp *dp_regs); 87*4882a593Smuzhiyun unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif /* _EXYNOS_DP_LOWLEVEL_H */ 90