xref: /OK3568_Linux_fs/u-boot/drivers/video/drm/rohm-bu18rl82.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <errno.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <video_bridge.h>
11*4882a593Smuzhiyun #include <asm/unaligned.h>
12*4882a593Smuzhiyun #include <linux/media-bus-format.h>
13*4882a593Smuzhiyun #include <power/regulator.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include "rockchip_bridge.h"
16*4882a593Smuzhiyun #include "rockchip_display.h"
17*4882a593Smuzhiyun #include "rockchip_panel.h"
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define BU18RL82_REG_RESET 0X000E
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define BU18RL82_SWRST_REG BIT(0)
22*4882a593Smuzhiyun #define BU18RL82_SWRST_EXCREG BIT(1)
23*4882a593Smuzhiyun #define BU18RL82_SWRST_ALL BIT(7)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun struct des_reg_sequence {
26*4882a593Smuzhiyun 	uint reg;
27*4882a593Smuzhiyun 	uint def;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct serdes_init_seq {
31*4882a593Smuzhiyun 	struct des_reg_sequence *reg_sequence;
32*4882a593Smuzhiyun 	uint reg_seq_cnt;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun struct bu18rl82_priv {
36*4882a593Smuzhiyun 	struct udevice *dev;
37*4882a593Smuzhiyun 	struct serdes_init_seq *serdes_init_seq;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
bu18rl82_bridge_reset(struct rockchip_bridge * bridge)40*4882a593Smuzhiyun static void bu18rl82_bridge_reset(struct rockchip_bridge *bridge)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	int ret = 0;
43*4882a593Smuzhiyun 	struct udevice *dev = bridge->dev;
44*4882a593Smuzhiyun 	struct udevice *bus = dev_get_parent(dev);
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	ret = dm_i2c_reg_write(dev, BU18RL82_REG_RESET,
47*4882a593Smuzhiyun 			       (BU18RL82_SWRST_REG | BU18RL82_SWRST_EXCREG | BU18RL82_SWRST_ALL));
48*4882a593Smuzhiyun 	if (ret < 0)
49*4882a593Smuzhiyun 		printf("failed to reset bu18rl82(%s) ret=%d\n", bus->name, ret);
50*4882a593Smuzhiyun 	mdelay(5);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
bu18rl82_serdes_init_sequence_write(struct bu18rl82_priv * priv)53*4882a593Smuzhiyun static int bu18rl82_serdes_init_sequence_write(struct bu18rl82_priv *priv)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	struct serdes_init_seq *serdes_init_seq = priv->serdes_init_seq;
56*4882a593Smuzhiyun 	struct des_reg_sequence *reg_sequence =  serdes_init_seq->reg_sequence;
57*4882a593Smuzhiyun 	uint cnt = serdes_init_seq->reg_seq_cnt;
58*4882a593Smuzhiyun 	struct udevice *dev = priv->dev;
59*4882a593Smuzhiyun 	uint i;
60*4882a593Smuzhiyun 	int ret = 0;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	for (i = 0; i < cnt; i++) {
63*4882a593Smuzhiyun 		ret = dm_i2c_reg_write(dev, reg_sequence[i].reg, reg_sequence[i].def);
64*4882a593Smuzhiyun 		if (ret < 0) {
65*4882a593Smuzhiyun 			dev_err(priv->dev, "failed write reg: 0x%04x value: 0x%04x\n",
66*4882a593Smuzhiyun 				reg_sequence[i].reg, reg_sequence[i].def);
67*4882a593Smuzhiyun 			break;
68*4882a593Smuzhiyun 		}
69*4882a593Smuzhiyun 	}
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun 	return ret;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun 
bu18rl82_bridge_enable(struct rockchip_bridge * bridge)74*4882a593Smuzhiyun static void bu18rl82_bridge_enable(struct rockchip_bridge *bridge)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct udevice *dev = bridge->dev;
77*4882a593Smuzhiyun 	struct bu18rl82_priv *priv = dev_get_priv(dev);
78*4882a593Smuzhiyun 	struct udevice *bus = dev_get_parent(dev);
79*4882a593Smuzhiyun 	int i;
80*4882a593Smuzhiyun 	int ret;
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 	for (i = 0; i < 10; i++) {
83*4882a593Smuzhiyun 		ret = bu18rl82_serdes_init_sequence_write(priv);
84*4882a593Smuzhiyun 		if (ret < 0) {
85*4882a593Smuzhiyun 			dev_err(priv->dev, "%s ret=%d\n", bus->name, ret);
86*4882a593Smuzhiyun 			continue;
87*4882a593Smuzhiyun 		}
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 		break;
90*4882a593Smuzhiyun 	}
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun static const struct rockchip_bridge_funcs bu18rl82_bridge_funcs = {
94*4882a593Smuzhiyun 	.enable = bu18rl82_bridge_enable,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
bu18rl82_parse_init_seq(struct udevice * dev,const u16 * data,int length,struct serdes_init_seq * seq)97*4882a593Smuzhiyun static int bu18rl82_parse_init_seq(struct udevice *dev, const u16 *data,
98*4882a593Smuzhiyun 				   int length, struct serdes_init_seq *seq)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun 	struct des_reg_sequence *reg_sequence;
101*4882a593Smuzhiyun 	u16 *buf, *d;
102*4882a593Smuzhiyun 	unsigned int i, cnt;
103*4882a593Smuzhiyun 	int ret;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	if (!seq)
106*4882a593Smuzhiyun 		return -EINVAL;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	buf = calloc(1, length);
109*4882a593Smuzhiyun 	if (!buf)
110*4882a593Smuzhiyun 		return -ENOMEM;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	memcpy(buf, data, length);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	d = buf;
115*4882a593Smuzhiyun 	cnt = length / 4;
116*4882a593Smuzhiyun 	seq->reg_seq_cnt = cnt;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	seq->reg_sequence = calloc(cnt, sizeof(struct des_reg_sequence));
119*4882a593Smuzhiyun 	if (!seq->reg_sequence) {
120*4882a593Smuzhiyun 		ret = -ENOMEM;
121*4882a593Smuzhiyun 		goto free_buf;
122*4882a593Smuzhiyun 	}
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	for (i = 0; i < cnt; i++) {
125*4882a593Smuzhiyun 		reg_sequence = &seq->reg_sequence[i];
126*4882a593Smuzhiyun 		reg_sequence->reg = get_unaligned_be16(&d[0]);
127*4882a593Smuzhiyun 		reg_sequence->def = get_unaligned_be16(&d[1]);
128*4882a593Smuzhiyun 		d += 2;
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	return 0;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun free_buf:
134*4882a593Smuzhiyun 	free(buf);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return ret;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
bu18rl82_get_init_seq(struct bu18rl82_priv * priv)139*4882a593Smuzhiyun static int bu18rl82_get_init_seq(struct bu18rl82_priv *priv)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	const void *data = NULL;
142*4882a593Smuzhiyun 	int len, err;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	data = dev_read_prop(priv->dev, "serdes-init-sequence", &len);
145*4882a593Smuzhiyun 	if (!data) {
146*4882a593Smuzhiyun 		printf("failed to get serdes-init-sequence\n");
147*4882a593Smuzhiyun 		return -EINVAL;
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	priv->serdes_init_seq = calloc(1, sizeof(*priv->serdes_init_seq));
151*4882a593Smuzhiyun 	if (!priv->serdes_init_seq)
152*4882a593Smuzhiyun 		return -ENOMEM;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	err = bu18rl82_parse_init_seq(priv->dev, data, len, priv->serdes_init_seq);
155*4882a593Smuzhiyun 	if (err) {
156*4882a593Smuzhiyun 		printf("failed to parse serdes-init-sequence\n");
157*4882a593Smuzhiyun 		goto free_init_seq;
158*4882a593Smuzhiyun 	}
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	return 0;
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun free_init_seq:
163*4882a593Smuzhiyun 	free(priv->serdes_init_seq);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return err;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
bu18rl82_probe(struct udevice * dev)168*4882a593Smuzhiyun static int bu18rl82_probe(struct udevice *dev)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	struct bu18rl82_priv *priv = dev_get_priv(dev);
171*4882a593Smuzhiyun 	struct rockchip_bridge *bridge;
172*4882a593Smuzhiyun 	int ret;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	ret = i2c_set_chip_offset_len(dev, 2);
175*4882a593Smuzhiyun 	if (ret)
176*4882a593Smuzhiyun 		return ret;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	priv->dev = dev;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	bridge = calloc(1, sizeof(*bridge));
181*4882a593Smuzhiyun 	if (!bridge)
182*4882a593Smuzhiyun 		return -ENOMEM;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	ret = bu18rl82_get_init_seq(priv);
185*4882a593Smuzhiyun 	if (ret)
186*4882a593Smuzhiyun 		goto free_bridge;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	dev->driver_data = (ulong)bridge;
189*4882a593Smuzhiyun 	bridge->dev = dev;
190*4882a593Smuzhiyun 	bridge->funcs = &bu18rl82_bridge_funcs;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	bu18rl82_bridge_reset(bridge);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	return 0;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun free_bridge:
197*4882a593Smuzhiyun 	free(bridge);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	return ret;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static const struct udevice_id bu18rl82_of_match[] = {
203*4882a593Smuzhiyun 	{ .compatible = "rohm,bu18rl82", },
204*4882a593Smuzhiyun 	{}
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun U_BOOT_DRIVER(bu18rl82) = {
208*4882a593Smuzhiyun 	.name = "bu18rl82",
209*4882a593Smuzhiyun 	.id = UCLASS_VIDEO_BRIDGE,
210*4882a593Smuzhiyun 	.of_match = bu18rl82_of_match,
211*4882a593Smuzhiyun 	.probe = bu18rl82_probe,
212*4882a593Smuzhiyun 	.priv_auto_alloc_size = sizeof(struct bu18rl82_priv),
213*4882a593Smuzhiyun };
214