1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ROCKCHIP_VOP_REG_H 8*4882a593Smuzhiyun #define _ROCKCHIP_VOP_REG_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* rk3288 register definition */ 11*4882a593Smuzhiyun #define RK3288_REG_CFG_DONE 0x0000 12*4882a593Smuzhiyun #define RK3288_VERSION_INFO 0x0004 13*4882a593Smuzhiyun #define RK3288_SYS_CTRL 0x0008 14*4882a593Smuzhiyun #define RK3288_SYS_CTRL1 0x000c 15*4882a593Smuzhiyun #define RK3288_DSP_CTRL0 0x0010 16*4882a593Smuzhiyun #define RK3288_DSP_CTRL1 0x0014 17*4882a593Smuzhiyun #define RK3288_DSP_BG 0x0018 18*4882a593Smuzhiyun #define RK3288_MCU_CTRL 0x001c 19*4882a593Smuzhiyun #define RK3288_INTR_CTRL0 0x0020 20*4882a593Smuzhiyun #define RK3288_INTR_CTRL1 0x0024 21*4882a593Smuzhiyun #define RK3288_WIN0_CTRL0 0x0030 22*4882a593Smuzhiyun #define RK3288_WIN0_CTRL1 0x0034 23*4882a593Smuzhiyun #define RK3288_WIN0_COLOR_KEY 0x0038 24*4882a593Smuzhiyun #define RK3288_WIN0_VIR 0x003c 25*4882a593Smuzhiyun #define RK3288_WIN0_YRGB_MST 0x0040 26*4882a593Smuzhiyun #define RK3288_WIN0_CBR_MST 0x0044 27*4882a593Smuzhiyun #define RK3288_WIN0_ACT_INFO 0x0048 28*4882a593Smuzhiyun #define RK3288_WIN0_DSP_INFO 0x004c 29*4882a593Smuzhiyun #define RK3288_WIN0_DSP_ST 0x0050 30*4882a593Smuzhiyun #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054 31*4882a593Smuzhiyun #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058 32*4882a593Smuzhiyun #define RK3288_WIN0_SCL_OFFSET 0x005c 33*4882a593Smuzhiyun #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 34*4882a593Smuzhiyun #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 35*4882a593Smuzhiyun #define RK3288_WIN0_FADING_CTRL 0x0068 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* win1 register */ 38*4882a593Smuzhiyun #define RK3288_WIN1_CTRL0 0x0070 39*4882a593Smuzhiyun #define RK3288_WIN1_CTRL1 0x0074 40*4882a593Smuzhiyun #define RK3288_WIN1_COLOR_KEY 0x0078 41*4882a593Smuzhiyun #define RK3288_WIN1_VIR 0x007c 42*4882a593Smuzhiyun #define RK3288_WIN1_YRGB_MST 0x0080 43*4882a593Smuzhiyun #define RK3288_WIN1_CBR_MST 0x0084 44*4882a593Smuzhiyun #define RK3288_WIN1_ACT_INFO 0x0088 45*4882a593Smuzhiyun #define RK3288_WIN1_DSP_INFO 0x008c 46*4882a593Smuzhiyun #define RK3288_WIN1_DSP_ST 0x0090 47*4882a593Smuzhiyun #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094 48*4882a593Smuzhiyun #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098 49*4882a593Smuzhiyun #define RK3288_WIN1_SCL_OFFSET 0x009c 50*4882a593Smuzhiyun #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0 51*4882a593Smuzhiyun #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4 52*4882a593Smuzhiyun #define RK3288_WIN1_FADING_CTRL 0x00a8 53*4882a593Smuzhiyun /* win2 register */ 54*4882a593Smuzhiyun #define RK3288_WIN2_CTRL0 0x00b0 55*4882a593Smuzhiyun #define RK3288_WIN2_CTRL1 0x00b4 56*4882a593Smuzhiyun #define RK3288_WIN2_VIR0_1 0x00b8 57*4882a593Smuzhiyun #define RK3288_WIN2_VIR2_3 0x00bc 58*4882a593Smuzhiyun #define RK3288_WIN2_MST0 0x00c0 59*4882a593Smuzhiyun #define RK3288_WIN2_DSP_INFO0 0x00c4 60*4882a593Smuzhiyun #define RK3288_WIN2_DSP_ST0 0x00c8 61*4882a593Smuzhiyun #define RK3288_WIN2_COLOR_KEY 0x00cc 62*4882a593Smuzhiyun #define RK3288_WIN2_MST1 0x00d0 63*4882a593Smuzhiyun #define RK3288_WIN2_DSP_INFO1 0x00d4 64*4882a593Smuzhiyun #define RK3288_WIN2_DSP_ST1 0x00d8 65*4882a593Smuzhiyun #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc 66*4882a593Smuzhiyun #define RK3288_WIN2_MST2 0x00e0 67*4882a593Smuzhiyun #define RK3288_WIN2_DSP_INFO2 0x00e4 68*4882a593Smuzhiyun #define RK3288_WIN2_DSP_ST2 0x00e8 69*4882a593Smuzhiyun #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec 70*4882a593Smuzhiyun #define RK3288_WIN2_MST3 0x00f0 71*4882a593Smuzhiyun #define RK3288_WIN2_DSP_INFO3 0x00f4 72*4882a593Smuzhiyun #define RK3288_WIN2_DSP_ST3 0x00f8 73*4882a593Smuzhiyun #define RK3288_WIN2_FADING_CTRL 0x00fc 74*4882a593Smuzhiyun /* win3 register */ 75*4882a593Smuzhiyun #define RK3288_WIN3_CTRL0 0x0100 76*4882a593Smuzhiyun #define RK3288_WIN3_CTRL1 0x0104 77*4882a593Smuzhiyun #define RK3288_WIN3_VIR0_1 0x0108 78*4882a593Smuzhiyun #define RK3288_WIN3_VIR2_3 0x010c 79*4882a593Smuzhiyun #define RK3288_WIN3_MST0 0x0110 80*4882a593Smuzhiyun #define RK3288_WIN3_DSP_INFO0 0x0114 81*4882a593Smuzhiyun #define RK3288_WIN3_DSP_ST0 0x0118 82*4882a593Smuzhiyun #define RK3288_WIN3_COLOR_KEY 0x011c 83*4882a593Smuzhiyun #define RK3288_WIN3_MST1 0x0120 84*4882a593Smuzhiyun #define RK3288_WIN3_DSP_INFO1 0x0124 85*4882a593Smuzhiyun #define RK3288_WIN3_DSP_ST1 0x0128 86*4882a593Smuzhiyun #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c 87*4882a593Smuzhiyun #define RK3288_WIN3_MST2 0x0130 88*4882a593Smuzhiyun #define RK3288_WIN3_DSP_INFO2 0x0134 89*4882a593Smuzhiyun #define RK3288_WIN3_DSP_ST2 0x0138 90*4882a593Smuzhiyun #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c 91*4882a593Smuzhiyun #define RK3288_WIN3_MST3 0x0140 92*4882a593Smuzhiyun #define RK3288_WIN3_DSP_INFO3 0x0144 93*4882a593Smuzhiyun #define RK3288_WIN3_DSP_ST3 0x0148 94*4882a593Smuzhiyun #define RK3288_WIN3_FADING_CTRL 0x014c 95*4882a593Smuzhiyun /* hwc register */ 96*4882a593Smuzhiyun #define RK3288_HWC_CTRL0 0x0150 97*4882a593Smuzhiyun #define RK3288_HWC_CTRL1 0x0154 98*4882a593Smuzhiyun #define RK3288_HWC_MST 0x0158 99*4882a593Smuzhiyun #define RK3288_HWC_DSP_ST 0x015c 100*4882a593Smuzhiyun #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160 101*4882a593Smuzhiyun #define RK3288_HWC_DST_ALPHA_CTRL 0x0164 102*4882a593Smuzhiyun #define RK3288_HWC_FADING_CTRL 0x0168 103*4882a593Smuzhiyun /* post process register */ 104*4882a593Smuzhiyun #define RK3288_POST_DSP_HACT_INFO 0x0170 105*4882a593Smuzhiyun #define RK3288_POST_DSP_VACT_INFO 0x0174 106*4882a593Smuzhiyun #define RK3288_POST_SCL_FACTOR_YRGB 0x0178 107*4882a593Smuzhiyun #define RK3288_POST_SCL_CTRL 0x0180 108*4882a593Smuzhiyun #define RK3288_POST_DSP_VACT_INFO_F1 0x0184 109*4882a593Smuzhiyun #define RK3288_DSP_HTOTAL_HS_END 0x0188 110*4882a593Smuzhiyun #define RK3288_DSP_HACT_ST_END 0x018c 111*4882a593Smuzhiyun #define RK3288_DSP_VTOTAL_VS_END 0x0190 112*4882a593Smuzhiyun #define RK3288_DSP_VACT_ST_END 0x0194 113*4882a593Smuzhiyun #define RK3288_DSP_VS_ST_END_F1 0x0198 114*4882a593Smuzhiyun #define RK3288_DSP_VACT_ST_END_F1 0x019c 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define RK3288_BCSH_COLOR_BAR 0x01b0 117*4882a593Smuzhiyun #define RK3288_BCSH_BCS 0x01b4 118*4882a593Smuzhiyun #define RK3288_BCSH_H 0x01b8 119*4882a593Smuzhiyun #define RK3288_GRF_SOC_CON15 0x03a4 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define RK3288_MCU_BYPASS_WPORT 0x2200 122*4882a593Smuzhiyun /* register definition end */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* rk3368 register definition */ 125*4882a593Smuzhiyun #define RK3368_REG_CFG_DONE 0x0000 126*4882a593Smuzhiyun #define RK3368_VERSION_INFO 0x0004 127*4882a593Smuzhiyun #define RK3368_SYS_CTRL 0x0008 128*4882a593Smuzhiyun #define RK3368_SYS_CTRL1 0x000c 129*4882a593Smuzhiyun #define RK3368_DSP_CTRL0 0x0010 130*4882a593Smuzhiyun #define RK3368_DSP_CTRL1 0x0014 131*4882a593Smuzhiyun #define RK3368_DSP_BG 0x0018 132*4882a593Smuzhiyun #define RK3368_MCU_CTRL 0x001c 133*4882a593Smuzhiyun #define RK3368_LINE_FLAG 0x0020 134*4882a593Smuzhiyun #define RK3368_INTR_EN 0x0024 135*4882a593Smuzhiyun #define RK3368_INTR_CLEAR 0x0028 136*4882a593Smuzhiyun #define RK3368_INTR_STATUS 0x002c 137*4882a593Smuzhiyun #define RK3368_WIN0_CTRL0 0x0030 138*4882a593Smuzhiyun #define RK3368_WIN0_CTRL1 0x0034 139*4882a593Smuzhiyun #define RK3368_WIN0_COLOR_KEY 0x0038 140*4882a593Smuzhiyun #define RK3368_WIN0_VIR 0x003c 141*4882a593Smuzhiyun #define RK3368_WIN0_YRGB_MST 0x0040 142*4882a593Smuzhiyun #define RK3368_WIN0_CBR_MST 0x0044 143*4882a593Smuzhiyun #define RK3368_WIN0_ACT_INFO 0x0048 144*4882a593Smuzhiyun #define RK3368_WIN0_DSP_INFO 0x004c 145*4882a593Smuzhiyun #define RK3368_WIN0_DSP_ST 0x0050 146*4882a593Smuzhiyun #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 147*4882a593Smuzhiyun #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 148*4882a593Smuzhiyun #define RK3368_WIN0_SCL_OFFSET 0x005c 149*4882a593Smuzhiyun #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 150*4882a593Smuzhiyun #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 151*4882a593Smuzhiyun #define RK3368_WIN0_FADING_CTRL 0x0068 152*4882a593Smuzhiyun #define RK3368_WIN0_CTRL2 0x006c 153*4882a593Smuzhiyun #define RK3368_WIN1_CTRL0 0x0070 154*4882a593Smuzhiyun #define RK3368_WIN1_CTRL1 0x0074 155*4882a593Smuzhiyun #define RK3368_WIN1_COLOR_KEY 0x0078 156*4882a593Smuzhiyun #define RK3368_WIN1_VIR 0x007c 157*4882a593Smuzhiyun #define RK3368_WIN1_YRGB_MST 0x0080 158*4882a593Smuzhiyun #define RK3368_WIN1_CBR_MST 0x0084 159*4882a593Smuzhiyun #define RK3368_WIN1_ACT_INFO 0x0088 160*4882a593Smuzhiyun #define RK3368_WIN1_DSP_INFO 0x008c 161*4882a593Smuzhiyun #define RK3368_WIN1_DSP_ST 0x0090 162*4882a593Smuzhiyun #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 163*4882a593Smuzhiyun #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 164*4882a593Smuzhiyun #define RK3368_WIN1_SCL_OFFSET 0x009c 165*4882a593Smuzhiyun #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 166*4882a593Smuzhiyun #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 167*4882a593Smuzhiyun #define RK3368_WIN1_FADING_CTRL 0x00a8 168*4882a593Smuzhiyun #define RK3368_WIN1_CTRL2 0x00ac 169*4882a593Smuzhiyun #define RK3368_WIN2_CTRL0 0x00b0 170*4882a593Smuzhiyun #define RK3368_WIN2_CTRL1 0x00b4 171*4882a593Smuzhiyun #define RK3368_WIN2_VIR0_1 0x00b8 172*4882a593Smuzhiyun #define RK3368_WIN2_VIR2_3 0x00bc 173*4882a593Smuzhiyun #define RK3368_WIN2_MST0 0x00c0 174*4882a593Smuzhiyun #define RK3368_WIN2_DSP_INFO0 0x00c4 175*4882a593Smuzhiyun #define RK3368_WIN2_DSP_ST0 0x00c8 176*4882a593Smuzhiyun #define RK3368_WIN2_COLOR_KEY 0x00cc 177*4882a593Smuzhiyun #define RK3368_WIN2_MST1 0x00d0 178*4882a593Smuzhiyun #define RK3368_WIN2_DSP_INFO1 0x00d4 179*4882a593Smuzhiyun #define RK3368_WIN2_DSP_ST1 0x00d8 180*4882a593Smuzhiyun #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc 181*4882a593Smuzhiyun #define RK3368_WIN2_MST2 0x00e0 182*4882a593Smuzhiyun #define RK3368_WIN2_DSP_INFO2 0x00e4 183*4882a593Smuzhiyun #define RK3368_WIN2_DSP_ST2 0x00e8 184*4882a593Smuzhiyun #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec 185*4882a593Smuzhiyun #define RK3368_WIN2_MST3 0x00f0 186*4882a593Smuzhiyun #define RK3368_WIN2_DSP_INFO3 0x00f4 187*4882a593Smuzhiyun #define RK3368_WIN2_DSP_ST3 0x00f8 188*4882a593Smuzhiyun #define RK3368_WIN2_FADING_CTRL 0x00fc 189*4882a593Smuzhiyun #define RK3368_WIN3_CTRL0 0x0100 190*4882a593Smuzhiyun #define RK3368_WIN3_CTRL1 0x0104 191*4882a593Smuzhiyun #define RK3368_WIN3_VIR0_1 0x0108 192*4882a593Smuzhiyun #define RK3368_WIN3_VIR2_3 0x010c 193*4882a593Smuzhiyun #define RK3368_WIN3_MST0 0x0110 194*4882a593Smuzhiyun #define RK3368_WIN3_DSP_INFO0 0x0114 195*4882a593Smuzhiyun #define RK3368_WIN3_DSP_ST0 0x0118 196*4882a593Smuzhiyun #define RK3368_WIN3_COLOR_KEY 0x011c 197*4882a593Smuzhiyun #define RK3368_WIN3_MST1 0x0120 198*4882a593Smuzhiyun #define RK3368_WIN3_DSP_INFO1 0x0124 199*4882a593Smuzhiyun #define RK3368_WIN3_DSP_ST1 0x0128 200*4882a593Smuzhiyun #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c 201*4882a593Smuzhiyun #define RK3368_WIN3_MST2 0x0130 202*4882a593Smuzhiyun #define RK3368_WIN3_DSP_INFO2 0x0134 203*4882a593Smuzhiyun #define RK3368_WIN3_DSP_ST2 0x0138 204*4882a593Smuzhiyun #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c 205*4882a593Smuzhiyun #define RK3368_WIN3_MST3 0x0140 206*4882a593Smuzhiyun #define RK3368_WIN3_DSP_INFO3 0x0144 207*4882a593Smuzhiyun #define RK3368_WIN3_DSP_ST3 0x0148 208*4882a593Smuzhiyun #define RK3368_WIN3_FADING_CTRL 0x014c 209*4882a593Smuzhiyun #define RK3368_HWC_CTRL0 0x0150 210*4882a593Smuzhiyun #define RK3368_HWC_CTRL1 0x0154 211*4882a593Smuzhiyun #define RK3368_HWC_MST 0x0158 212*4882a593Smuzhiyun #define RK3368_HWC_DSP_ST 0x015c 213*4882a593Smuzhiyun #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 214*4882a593Smuzhiyun #define RK3368_HWC_DST_ALPHA_CTRL 0x0164 215*4882a593Smuzhiyun #define RK3368_HWC_FADING_CTRL 0x0168 216*4882a593Smuzhiyun #define RK3368_HWC_RESERVED1 0x016c 217*4882a593Smuzhiyun #define RK3368_POST_DSP_HACT_INFO 0x0170 218*4882a593Smuzhiyun #define RK3368_POST_DSP_VACT_INFO 0x0174 219*4882a593Smuzhiyun #define RK3368_POST_SCL_FACTOR_YRGB 0x0178 220*4882a593Smuzhiyun #define RK3368_POST_RESERVED 0x017c 221*4882a593Smuzhiyun #define RK3368_POST_SCL_CTRL 0x0180 222*4882a593Smuzhiyun #define RK3368_POST_DSP_VACT_INFO_F1 0x0184 223*4882a593Smuzhiyun #define RK3368_DSP_HTOTAL_HS_END 0x0188 224*4882a593Smuzhiyun #define RK3368_DSP_HACT_ST_END 0x018c 225*4882a593Smuzhiyun #define RK3368_DSP_VTOTAL_VS_END 0x0190 226*4882a593Smuzhiyun #define RK3368_DSP_VACT_ST_END 0x0194 227*4882a593Smuzhiyun #define RK3368_DSP_VS_ST_END_F1 0x0198 228*4882a593Smuzhiyun #define RK3368_DSP_VACT_ST_END_F1 0x019c 229*4882a593Smuzhiyun #define RK3368_PWM_CTRL 0x01a0 230*4882a593Smuzhiyun #define RK3368_PWM_PERIOD_HPR 0x01a4 231*4882a593Smuzhiyun #define RK3368_PWM_DUTY_LPR 0x01a8 232*4882a593Smuzhiyun #define RK3368_PWM_CNT 0x01ac 233*4882a593Smuzhiyun #define RK3368_BCSH_COLOR_BAR 0x01b0 234*4882a593Smuzhiyun #define RK3368_BCSH_BCS 0x01b4 235*4882a593Smuzhiyun #define RK3368_BCSH_H 0x01b8 236*4882a593Smuzhiyun #define RK3368_BCSH_CTRL 0x01bc 237*4882a593Smuzhiyun #define RK3368_CABC_CTRL0 0x01c0 238*4882a593Smuzhiyun #define RK3368_CABC_CTRL1 0x01c4 239*4882a593Smuzhiyun #define RK3368_CABC_CTRL2 0x01c8 240*4882a593Smuzhiyun #define RK3368_CABC_CTRL3 0x01cc 241*4882a593Smuzhiyun #define RK3368_CABC_GAUSS_LINE0_0 0x01d0 242*4882a593Smuzhiyun #define RK3368_CABC_GAUSS_LINE0_1 0x01d4 243*4882a593Smuzhiyun #define RK3368_CABC_GAUSS_LINE1_0 0x01d8 244*4882a593Smuzhiyun #define RK3368_CABC_GAUSS_LINE1_1 0x01dc 245*4882a593Smuzhiyun #define RK3368_CABC_GAUSS_LINE2_0 0x01e0 246*4882a593Smuzhiyun #define RK3368_CABC_GAUSS_LINE2_1 0x01e4 247*4882a593Smuzhiyun #define RK3368_FRC_LOWER01_0 0x01e8 248*4882a593Smuzhiyun #define RK3368_FRC_LOWER01_1 0x01ec 249*4882a593Smuzhiyun #define RK3368_FRC_LOWER10_0 0x01f0 250*4882a593Smuzhiyun #define RK3368_FRC_LOWER10_1 0x01f4 251*4882a593Smuzhiyun #define RK3368_FRC_LOWER11_0 0x01f8 252*4882a593Smuzhiyun #define RK3368_FRC_LOWER11_1 0x01fc 253*4882a593Smuzhiyun #define RK3368_IFBDC_CTRL 0x0200 254*4882a593Smuzhiyun #define RK3368_IFBDC_TILES_NUM 0x0204 255*4882a593Smuzhiyun #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 256*4882a593Smuzhiyun #define RK3368_IFBDC_BASE_ADDR 0x020c 257*4882a593Smuzhiyun #define RK3368_IFBDC_MB_SIZE 0x0210 258*4882a593Smuzhiyun #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 259*4882a593Smuzhiyun #define RK3368_IFBDC_VIR 0x0220 260*4882a593Smuzhiyun #define RK3368_IFBDC_DEBUG0 0x0230 261*4882a593Smuzhiyun #define RK3368_IFBDC_DEBUG1 0x0234 262*4882a593Smuzhiyun #define RK3368_LATENCY_CTRL0 0x0250 263*4882a593Smuzhiyun #define RK3368_RD_MAX_LATENCY_NUM0 0x0254 264*4882a593Smuzhiyun #define RK3368_RD_LATENCY_THR_NUM0 0x0258 265*4882a593Smuzhiyun #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c 266*4882a593Smuzhiyun #define RK3368_WIN0_DSP_BG 0x0260 267*4882a593Smuzhiyun #define RK3368_WIN1_DSP_BG 0x0264 268*4882a593Smuzhiyun #define RK3368_WIN2_DSP_BG 0x0268 269*4882a593Smuzhiyun #define RK3368_WIN3_DSP_BG 0x026c 270*4882a593Smuzhiyun #define RK3368_SCAN_LINE_NUM 0x0270 271*4882a593Smuzhiyun #define RK3368_CABC_DEBUG0 0x0274 272*4882a593Smuzhiyun #define RK3368_CABC_DEBUG1 0x0278 273*4882a593Smuzhiyun #define RK3368_CABC_DEBUG2 0x027c 274*4882a593Smuzhiyun #define RK3368_DBG_REG_000 0x0280 275*4882a593Smuzhiyun #define RK3368_DBG_REG_001 0x0284 276*4882a593Smuzhiyun #define RK3368_DBG_REG_002 0x0288 277*4882a593Smuzhiyun #define RK3368_DBG_REG_003 0x028c 278*4882a593Smuzhiyun #define RK3368_DBG_REG_004 0x0290 279*4882a593Smuzhiyun #define RK3368_DBG_REG_005 0x0294 280*4882a593Smuzhiyun #define RK3368_DBG_REG_006 0x0298 281*4882a593Smuzhiyun #define RK3368_DBG_REG_007 0x029c 282*4882a593Smuzhiyun #define RK3368_DBG_REG_008 0x02a0 283*4882a593Smuzhiyun #define RK3368_DBG_REG_016 0x02c0 284*4882a593Smuzhiyun #define RK3368_DBG_REG_017 0x02c4 285*4882a593Smuzhiyun #define RK3368_DBG_REG_018 0x02c8 286*4882a593Smuzhiyun #define RK3368_DBG_REG_019 0x02cc 287*4882a593Smuzhiyun #define RK3368_DBG_REG_020 0x02d0 288*4882a593Smuzhiyun #define RK3368_DBG_REG_021 0x02d4 289*4882a593Smuzhiyun #define RK3368_DBG_REG_022 0x02d8 290*4882a593Smuzhiyun #define RK3368_DBG_REG_023 0x02dc 291*4882a593Smuzhiyun #define RK3368_DBG_REG_028 0x02f0 292*4882a593Smuzhiyun #define RK3368_MMU_DTE_ADDR 0x0300 293*4882a593Smuzhiyun #define RK3368_MMU_STATUS 0x0304 294*4882a593Smuzhiyun #define RK3368_MMU_COMMAND 0x0308 295*4882a593Smuzhiyun #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c 296*4882a593Smuzhiyun #define RK3368_MMU_ZAP_ONE_LINE 0x0310 297*4882a593Smuzhiyun #define RK3368_MMU_INT_RAWSTAT 0x0314 298*4882a593Smuzhiyun #define RK3368_MMU_INT_CLEAR 0x0318 299*4882a593Smuzhiyun #define RK3368_MMU_INT_MASK 0x031c 300*4882a593Smuzhiyun #define RK3368_MMU_INT_STATUS 0x0320 301*4882a593Smuzhiyun #define RK3368_MMU_AUTO_GATING 0x0324 302*4882a593Smuzhiyun #define RK3368_WIN2_LUT_ADDR 0x0400 303*4882a593Smuzhiyun #define RK3368_WIN3_LUT_ADDR 0x0800 304*4882a593Smuzhiyun #define RK3368_HWC_LUT_ADDR 0x0c00 305*4882a593Smuzhiyun #define RK3368_GAMMA_LUT_ADDR 0x1000 306*4882a593Smuzhiyun #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 307*4882a593Smuzhiyun #define RK3368_MCU_BYPASS_WPORT 0x2200 308*4882a593Smuzhiyun #define RK3368_MCU_BYPASS_RPORT 0x2300 309*4882a593Smuzhiyun #define RK3368_GRF_SOC_CON6 0x0418 310*4882a593Smuzhiyun /* rk3368 register definition end */ 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun #define RK3366_REG_CFG_DONE 0x0000 313*4882a593Smuzhiyun #define RK3366_VERSION_INFO 0x0004 314*4882a593Smuzhiyun #define RK3366_SYS_CTRL 0x0008 315*4882a593Smuzhiyun #define RK3366_SYS_CTRL1 0x000c 316*4882a593Smuzhiyun #define RK3366_DSP_CTRL0 0x0010 317*4882a593Smuzhiyun #define RK3366_DSP_CTRL1 0x0014 318*4882a593Smuzhiyun #define RK3366_DSP_BG 0x0018 319*4882a593Smuzhiyun #define RK3366_MCU_CTRL 0x001c 320*4882a593Smuzhiyun #define RK3366_WB_CTRL0 0x0020 321*4882a593Smuzhiyun #define RK3366_WB_CTRL1 0x0024 322*4882a593Smuzhiyun #define RK3366_WB_YRGB_MST 0x0028 323*4882a593Smuzhiyun #define RK3366_WB_CBR_MST 0x002c 324*4882a593Smuzhiyun #define RK3366_WIN0_CTRL0 0x0030 325*4882a593Smuzhiyun #define RK3366_WIN0_CTRL1 0x0034 326*4882a593Smuzhiyun #define RK3366_WIN0_COLOR_KEY 0x0038 327*4882a593Smuzhiyun #define RK3366_WIN0_VIR 0x003c 328*4882a593Smuzhiyun #define RK3366_WIN0_YRGB_MST 0x0040 329*4882a593Smuzhiyun #define RK3366_WIN0_CBR_MST 0x0044 330*4882a593Smuzhiyun #define RK3366_WIN0_ACT_INFO 0x0048 331*4882a593Smuzhiyun #define RK3366_WIN0_DSP_INFO 0x004c 332*4882a593Smuzhiyun #define RK3366_WIN0_DSP_ST 0x0050 333*4882a593Smuzhiyun #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 334*4882a593Smuzhiyun #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 335*4882a593Smuzhiyun #define RK3366_WIN0_SCL_OFFSET 0x005c 336*4882a593Smuzhiyun #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 337*4882a593Smuzhiyun #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 338*4882a593Smuzhiyun #define RK3366_WIN0_FADING_CTRL 0x0068 339*4882a593Smuzhiyun #define RK3366_WIN0_CTRL2 0x006c 340*4882a593Smuzhiyun #define RK3366_WIN1_CTRL0 0x0070 341*4882a593Smuzhiyun #define RK3366_WIN1_CTRL1 0x0074 342*4882a593Smuzhiyun #define RK3366_WIN1_COLOR_KEY 0x0078 343*4882a593Smuzhiyun #define RK3366_WIN1_VIR 0x007c 344*4882a593Smuzhiyun #define RK3366_WIN1_YRGB_MST 0x0080 345*4882a593Smuzhiyun #define RK3366_WIN1_CBR_MST 0x0084 346*4882a593Smuzhiyun #define RK3366_WIN1_ACT_INFO 0x0088 347*4882a593Smuzhiyun #define RK3366_WIN1_DSP_INFO 0x008c 348*4882a593Smuzhiyun #define RK3366_WIN1_DSP_ST 0x0090 349*4882a593Smuzhiyun #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 350*4882a593Smuzhiyun #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 351*4882a593Smuzhiyun #define RK3366_WIN1_SCL_OFFSET 0x009c 352*4882a593Smuzhiyun #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 353*4882a593Smuzhiyun #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 354*4882a593Smuzhiyun #define RK3366_WIN1_FADING_CTRL 0x00a8 355*4882a593Smuzhiyun #define RK3366_WIN1_CTRL2 0x00ac 356*4882a593Smuzhiyun #define RK3366_WIN2_CTRL0 0x00b0 357*4882a593Smuzhiyun #define RK3366_WIN2_CTRL1 0x00b4 358*4882a593Smuzhiyun #define RK3366_WIN2_VIR0_1 0x00b8 359*4882a593Smuzhiyun #define RK3366_WIN2_VIR2_3 0x00bc 360*4882a593Smuzhiyun #define RK3366_WIN2_MST0 0x00c0 361*4882a593Smuzhiyun #define RK3366_WIN2_DSP_INFO0 0x00c4 362*4882a593Smuzhiyun #define RK3366_WIN2_DSP_ST0 0x00c8 363*4882a593Smuzhiyun #define RK3366_WIN2_COLOR_KEY 0x00cc 364*4882a593Smuzhiyun #define RK3366_WIN2_MST1 0x00d0 365*4882a593Smuzhiyun #define RK3366_WIN2_DSP_INFO1 0x00d4 366*4882a593Smuzhiyun #define RK3366_WIN2_DSP_ST1 0x00d8 367*4882a593Smuzhiyun #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc 368*4882a593Smuzhiyun #define RK3366_WIN2_MST2 0x00e0 369*4882a593Smuzhiyun #define RK3366_WIN2_DSP_INFO2 0x00e4 370*4882a593Smuzhiyun #define RK3366_WIN2_DSP_ST2 0x00e8 371*4882a593Smuzhiyun #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec 372*4882a593Smuzhiyun #define RK3366_WIN2_MST3 0x00f0 373*4882a593Smuzhiyun #define RK3366_WIN2_DSP_INFO3 0x00f4 374*4882a593Smuzhiyun #define RK3366_WIN2_DSP_ST3 0x00f8 375*4882a593Smuzhiyun #define RK3366_WIN2_FADING_CTRL 0x00fc 376*4882a593Smuzhiyun #define RK3366_WIN3_CTRL0 0x0100 377*4882a593Smuzhiyun #define RK3366_WIN3_CTRL1 0x0104 378*4882a593Smuzhiyun #define RK3366_WIN3_VIR0_1 0x0108 379*4882a593Smuzhiyun #define RK3366_WIN3_VIR2_3 0x010c 380*4882a593Smuzhiyun #define RK3366_WIN3_MST0 0x0110 381*4882a593Smuzhiyun #define RK3366_WIN3_DSP_INFO0 0x0114 382*4882a593Smuzhiyun #define RK3366_WIN3_DSP_ST0 0x0118 383*4882a593Smuzhiyun #define RK3366_WIN3_COLOR_KEY 0x011c 384*4882a593Smuzhiyun #define RK3366_WIN3_MST1 0x0120 385*4882a593Smuzhiyun #define RK3366_WIN3_DSP_INFO1 0x0124 386*4882a593Smuzhiyun #define RK3366_WIN3_DSP_ST1 0x0128 387*4882a593Smuzhiyun #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c 388*4882a593Smuzhiyun #define RK3366_WIN3_MST2 0x0130 389*4882a593Smuzhiyun #define RK3366_WIN3_DSP_INFO2 0x0134 390*4882a593Smuzhiyun #define RK3366_WIN3_DSP_ST2 0x0138 391*4882a593Smuzhiyun #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c 392*4882a593Smuzhiyun #define RK3366_WIN3_MST3 0x0140 393*4882a593Smuzhiyun #define RK3366_WIN3_DSP_INFO3 0x0144 394*4882a593Smuzhiyun #define RK3366_WIN3_DSP_ST3 0x0148 395*4882a593Smuzhiyun #define RK3366_WIN3_FADING_CTRL 0x014c 396*4882a593Smuzhiyun #define RK3366_HWC_CTRL0 0x0150 397*4882a593Smuzhiyun #define RK3366_HWC_CTRL1 0x0154 398*4882a593Smuzhiyun #define RK3366_HWC_MST 0x0158 399*4882a593Smuzhiyun #define RK3366_HWC_DSP_ST 0x015c 400*4882a593Smuzhiyun #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 401*4882a593Smuzhiyun #define RK3366_HWC_DST_ALPHA_CTRL 0x0164 402*4882a593Smuzhiyun #define RK3366_HWC_FADING_CTRL 0x0168 403*4882a593Smuzhiyun #define RK3366_HWC_RESERVED1 0x016c 404*4882a593Smuzhiyun #define RK3366_POST_DSP_HACT_INFO 0x0170 405*4882a593Smuzhiyun #define RK3366_POST_DSP_VACT_INFO 0x0174 406*4882a593Smuzhiyun #define RK3366_POST_SCL_FACTOR_YRGB 0x0178 407*4882a593Smuzhiyun #define RK3366_POST_RESERVED 0x017c 408*4882a593Smuzhiyun #define RK3366_POST_SCL_CTRL 0x0180 409*4882a593Smuzhiyun #define RK3366_POST_DSP_VACT_INFO_F1 0x0184 410*4882a593Smuzhiyun #define RK3366_DSP_HTOTAL_HS_END 0x0188 411*4882a593Smuzhiyun #define RK3366_DSP_HACT_ST_END 0x018c 412*4882a593Smuzhiyun #define RK3366_DSP_VTOTAL_VS_END 0x0190 413*4882a593Smuzhiyun #define RK3366_DSP_VACT_ST_END 0x0194 414*4882a593Smuzhiyun #define RK3366_DSP_VS_ST_END_F1 0x0198 415*4882a593Smuzhiyun #define RK3366_DSP_VACT_ST_END_F1 0x019c 416*4882a593Smuzhiyun #define RK3366_PWM_CTRL 0x01a0 417*4882a593Smuzhiyun #define RK3366_PWM_PERIOD_HPR 0x01a4 418*4882a593Smuzhiyun #define RK3366_PWM_DUTY_LPR 0x01a8 419*4882a593Smuzhiyun #define RK3366_PWM_CNT 0x01ac 420*4882a593Smuzhiyun #define RK3366_BCSH_COLOR_BAR 0x01b0 421*4882a593Smuzhiyun #define RK3366_BCSH_BCS 0x01b4 422*4882a593Smuzhiyun #define RK3366_BCSH_H 0x01b8 423*4882a593Smuzhiyun #define RK3366_BCSH_CTRL 0x01bc 424*4882a593Smuzhiyun #define RK3366_CABC_CTRL0 0x01c0 425*4882a593Smuzhiyun #define RK3366_CABC_CTRL1 0x01c4 426*4882a593Smuzhiyun #define RK3366_CABC_CTRL2 0x01c8 427*4882a593Smuzhiyun #define RK3366_CABC_CTRL3 0x01cc 428*4882a593Smuzhiyun #define RK3366_CABC_GAUSS_LINE0_0 0x01d0 429*4882a593Smuzhiyun #define RK3366_CABC_GAUSS_LINE0_1 0x01d4 430*4882a593Smuzhiyun #define RK3366_CABC_GAUSS_LINE1_0 0x01d8 431*4882a593Smuzhiyun #define RK3366_CABC_GAUSS_LINE1_1 0x01dc 432*4882a593Smuzhiyun #define RK3366_CABC_GAUSS_LINE2_0 0x01e0 433*4882a593Smuzhiyun #define RK3366_CABC_GAUSS_LINE2_1 0x01e4 434*4882a593Smuzhiyun #define RK3366_FRC_LOWER01_0 0x01e8 435*4882a593Smuzhiyun #define RK3366_FRC_LOWER01_1 0x01ec 436*4882a593Smuzhiyun #define RK3366_FRC_LOWER10_0 0x01f0 437*4882a593Smuzhiyun #define RK3366_FRC_LOWER10_1 0x01f4 438*4882a593Smuzhiyun #define RK3366_FRC_LOWER11_0 0x01f8 439*4882a593Smuzhiyun #define RK3366_FRC_LOWER11_1 0x01fc 440*4882a593Smuzhiyun #define RK3366_INTR_EN0 0x0280 441*4882a593Smuzhiyun #define RK3366_INTR_CLEAR0 0x0284 442*4882a593Smuzhiyun #define RK3366_INTR_STATUS0 0x0288 443*4882a593Smuzhiyun #define RK3366_INTR_RAW_STATUS0 0x028c 444*4882a593Smuzhiyun #define RK3366_INTR_EN1 0x0290 445*4882a593Smuzhiyun #define RK3366_INTR_CLEAR1 0x0294 446*4882a593Smuzhiyun #define RK3366_INTR_STATUS1 0x0298 447*4882a593Smuzhiyun #define RK3366_INTR_RAW_STATUS1 0x029c 448*4882a593Smuzhiyun #define RK3366_LINE_FLAG 0x02a0 449*4882a593Smuzhiyun #define RK3366_VOP_STATUS 0x02a4 450*4882a593Smuzhiyun #define RK3366_BLANKING_VALUE 0x02a8 451*4882a593Smuzhiyun #define RK3366_WIN0_DSP_BG 0x02b0 452*4882a593Smuzhiyun #define RK3366_WIN1_DSP_BG 0x02b4 453*4882a593Smuzhiyun #define RK3366_WIN2_DSP_BG 0x02b8 454*4882a593Smuzhiyun #define RK3366_WIN3_DSP_BG 0x02bc 455*4882a593Smuzhiyun #define RK3366_WIN2_LUT_ADDR 0x0400 456*4882a593Smuzhiyun #define RK3366_WIN3_LUT_ADDR 0x0800 457*4882a593Smuzhiyun #define RK3366_HWC_LUT_ADDR 0x0c00 458*4882a593Smuzhiyun #define RK3366_GAMMA0_LUT_ADDR 0x1000 459*4882a593Smuzhiyun #define RK3366_GAMMA1_LUT_ADDR 0x1400 460*4882a593Smuzhiyun #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 461*4882a593Smuzhiyun #define RK3366_MCU_BYPASS_WPORT 0x2200 462*4882a593Smuzhiyun #define RK3366_MCU_BYPASS_RPORT 0x2300 463*4882a593Smuzhiyun #define RK3366_MMU_DTE_ADDR 0x2400 464*4882a593Smuzhiyun #define RK3366_MMU_STATUS 0x2404 465*4882a593Smuzhiyun #define RK3366_MMU_COMMAND 0x2408 466*4882a593Smuzhiyun #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c 467*4882a593Smuzhiyun #define RK3366_MMU_ZAP_ONE_LINE 0x2410 468*4882a593Smuzhiyun #define RK3366_MMU_INT_RAWSTAT 0x2414 469*4882a593Smuzhiyun #define RK3366_MMU_INT_CLEAR 0x2418 470*4882a593Smuzhiyun #define RK3366_MMU_INT_MASK 0x241c 471*4882a593Smuzhiyun #define RK3366_MMU_INT_STATUS 0x2420 472*4882a593Smuzhiyun #define RK3366_MMU_AUTO_GATING 0x2424 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun /* rk3399 register definition */ 475*4882a593Smuzhiyun #define RK3399_REG_CFG_DONE 0x0000 476*4882a593Smuzhiyun #define RK3399_VERSION_INFO 0x0004 477*4882a593Smuzhiyun #define RK3399_SYS_CTRL 0x0008 478*4882a593Smuzhiyun #define RK3399_SYS_CTRL1 0x000c 479*4882a593Smuzhiyun #define RK3399_DSP_CTRL0 0x0010 480*4882a593Smuzhiyun #define RK3399_DSP_CTRL1 0x0014 481*4882a593Smuzhiyun #define RK3399_DSP_BG 0x0018 482*4882a593Smuzhiyun #define RK3399_MCU_CTRL 0x001c 483*4882a593Smuzhiyun #define RK3399_WB_CTRL0 0x0020 484*4882a593Smuzhiyun #define RK3399_WB_CTRL1 0x0024 485*4882a593Smuzhiyun #define RK3399_WB_YRGB_MST 0x0028 486*4882a593Smuzhiyun #define RK3399_WB_CBR_MST 0x002c 487*4882a593Smuzhiyun #define RK3399_WIN0_CTRL0 0x0030 488*4882a593Smuzhiyun #define RK3399_WIN0_CTRL1 0x0034 489*4882a593Smuzhiyun #define RK3399_WIN0_COLOR_KEY 0x0038 490*4882a593Smuzhiyun #define RK3399_WIN0_VIR 0x003c 491*4882a593Smuzhiyun #define RK3399_WIN0_YRGB_MST 0x0040 492*4882a593Smuzhiyun #define RK3399_WIN0_CBR_MST 0x0044 493*4882a593Smuzhiyun #define RK3399_WIN0_ACT_INFO 0x0048 494*4882a593Smuzhiyun #define RK3399_WIN0_DSP_INFO 0x004c 495*4882a593Smuzhiyun #define RK3399_WIN0_DSP_ST 0x0050 496*4882a593Smuzhiyun #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 497*4882a593Smuzhiyun #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 498*4882a593Smuzhiyun #define RK3399_WIN0_SCL_OFFSET 0x005c 499*4882a593Smuzhiyun #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 500*4882a593Smuzhiyun #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 501*4882a593Smuzhiyun #define RK3399_WIN0_FADING_CTRL 0x0068 502*4882a593Smuzhiyun #define RK3399_WIN0_CTRL2 0x006c 503*4882a593Smuzhiyun #define RK3399_WIN1_CTRL0 0x0070 504*4882a593Smuzhiyun #define RK3399_WIN1_CTRL1 0x0074 505*4882a593Smuzhiyun #define RK3399_WIN1_COLOR_KEY 0x0078 506*4882a593Smuzhiyun #define RK3399_WIN1_VIR 0x007c 507*4882a593Smuzhiyun #define RK3399_WIN1_YRGB_MST 0x0080 508*4882a593Smuzhiyun #define RK3399_WIN1_CBR_MST 0x0084 509*4882a593Smuzhiyun #define RK3399_WIN1_ACT_INFO 0x0088 510*4882a593Smuzhiyun #define RK3399_WIN1_DSP_INFO 0x008c 511*4882a593Smuzhiyun #define RK3399_WIN1_DSP_ST 0x0090 512*4882a593Smuzhiyun #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 513*4882a593Smuzhiyun #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 514*4882a593Smuzhiyun #define RK3399_WIN1_SCL_OFFSET 0x009c 515*4882a593Smuzhiyun #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 516*4882a593Smuzhiyun #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 517*4882a593Smuzhiyun #define RK3399_WIN1_FADING_CTRL 0x00a8 518*4882a593Smuzhiyun #define RK3399_WIN1_CTRL2 0x00ac 519*4882a593Smuzhiyun #define RK3399_WIN2_CTRL0 0x00b0 520*4882a593Smuzhiyun #define RK3399_WIN2_CTRL1 0x00b4 521*4882a593Smuzhiyun #define RK3399_WIN2_VIR0_1 0x00b8 522*4882a593Smuzhiyun #define RK3399_WIN2_VIR2_3 0x00bc 523*4882a593Smuzhiyun #define RK3399_WIN2_MST0 0x00c0 524*4882a593Smuzhiyun #define RK3399_WIN2_DSP_INFO0 0x00c4 525*4882a593Smuzhiyun #define RK3399_WIN2_DSP_ST0 0x00c8 526*4882a593Smuzhiyun #define RK3399_WIN2_COLOR_KEY 0x00cc 527*4882a593Smuzhiyun #define RK3399_WIN2_MST1 0x00d0 528*4882a593Smuzhiyun #define RK3399_WIN2_DSP_INFO1 0x00d4 529*4882a593Smuzhiyun #define RK3399_WIN2_DSP_ST1 0x00d8 530*4882a593Smuzhiyun #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc 531*4882a593Smuzhiyun #define RK3399_WIN2_MST2 0x00e0 532*4882a593Smuzhiyun #define RK3399_WIN2_DSP_INFO2 0x00e4 533*4882a593Smuzhiyun #define RK3399_WIN2_DSP_ST2 0x00e8 534*4882a593Smuzhiyun #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec 535*4882a593Smuzhiyun #define RK3399_WIN2_MST3 0x00f0 536*4882a593Smuzhiyun #define RK3399_WIN2_DSP_INFO3 0x00f4 537*4882a593Smuzhiyun #define RK3399_WIN2_DSP_ST3 0x00f8 538*4882a593Smuzhiyun #define RK3399_WIN2_FADING_CTRL 0x00fc 539*4882a593Smuzhiyun #define RK3399_WIN3_CTRL0 0x0100 540*4882a593Smuzhiyun #define RK3399_WIN3_CTRL1 0x0104 541*4882a593Smuzhiyun #define RK3399_WIN3_VIR0_1 0x0108 542*4882a593Smuzhiyun #define RK3399_WIN3_VIR2_3 0x010c 543*4882a593Smuzhiyun #define RK3399_WIN3_MST0 0x0110 544*4882a593Smuzhiyun #define RK3399_WIN3_DSP_INFO0 0x0114 545*4882a593Smuzhiyun #define RK3399_WIN3_DSP_ST0 0x0118 546*4882a593Smuzhiyun #define RK3399_WIN3_COLOR_KEY 0x011c 547*4882a593Smuzhiyun #define RK3399_WIN3_MST1 0x0120 548*4882a593Smuzhiyun #define RK3399_WIN3_DSP_INFO1 0x0124 549*4882a593Smuzhiyun #define RK3399_WIN3_DSP_ST1 0x0128 550*4882a593Smuzhiyun #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c 551*4882a593Smuzhiyun #define RK3399_WIN3_MST2 0x0130 552*4882a593Smuzhiyun #define RK3399_WIN3_DSP_INFO2 0x0134 553*4882a593Smuzhiyun #define RK3399_WIN3_DSP_ST2 0x0138 554*4882a593Smuzhiyun #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c 555*4882a593Smuzhiyun #define RK3399_WIN3_MST3 0x0140 556*4882a593Smuzhiyun #define RK3399_WIN3_DSP_INFO3 0x0144 557*4882a593Smuzhiyun #define RK3399_WIN3_DSP_ST3 0x0148 558*4882a593Smuzhiyun #define RK3399_WIN3_FADING_CTRL 0x014c 559*4882a593Smuzhiyun #define RK3399_HWC_CTRL0 0x0150 560*4882a593Smuzhiyun #define RK3399_HWC_CTRL1 0x0154 561*4882a593Smuzhiyun #define RK3399_HWC_MST 0x0158 562*4882a593Smuzhiyun #define RK3399_HWC_DSP_ST 0x015c 563*4882a593Smuzhiyun #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 564*4882a593Smuzhiyun #define RK3399_HWC_DST_ALPHA_CTRL 0x0164 565*4882a593Smuzhiyun #define RK3399_HWC_FADING_CTRL 0x0168 566*4882a593Smuzhiyun #define RK3399_HWC_RESERVED1 0x016c 567*4882a593Smuzhiyun #define RK3399_POST_DSP_HACT_INFO 0x0170 568*4882a593Smuzhiyun #define RK3399_POST_DSP_VACT_INFO 0x0174 569*4882a593Smuzhiyun #define RK3399_POST_SCL_FACTOR_YRGB 0x0178 570*4882a593Smuzhiyun #define RK3399_POST_RESERVED 0x017c 571*4882a593Smuzhiyun #define RK3399_POST_SCL_CTRL 0x0180 572*4882a593Smuzhiyun #define RK3399_POST_DSP_VACT_INFO_F1 0x0184 573*4882a593Smuzhiyun #define RK3399_DSP_HTOTAL_HS_END 0x0188 574*4882a593Smuzhiyun #define RK3399_DSP_HACT_ST_END 0x018c 575*4882a593Smuzhiyun #define RK3399_DSP_VTOTAL_VS_END 0x0190 576*4882a593Smuzhiyun #define RK3399_DSP_VACT_ST_END 0x0194 577*4882a593Smuzhiyun #define RK3399_DSP_VS_ST_END_F1 0x0198 578*4882a593Smuzhiyun #define RK3399_DSP_VACT_ST_END_F1 0x019c 579*4882a593Smuzhiyun #define RK3399_PWM_CTRL 0x01a0 580*4882a593Smuzhiyun #define RK3399_PWM_PERIOD_HPR 0x01a4 581*4882a593Smuzhiyun #define RK3399_PWM_DUTY_LPR 0x01a8 582*4882a593Smuzhiyun #define RK3399_PWM_CNT 0x01ac 583*4882a593Smuzhiyun #define RK3399_BCSH_COLOR_BAR 0x01b0 584*4882a593Smuzhiyun #define RK3399_BCSH_BCS 0x01b4 585*4882a593Smuzhiyun #define RK3399_BCSH_H 0x01b8 586*4882a593Smuzhiyun #define RK3399_BCSH_CTRL 0x01bc 587*4882a593Smuzhiyun #define RK3399_CABC_CTRL0 0x01c0 588*4882a593Smuzhiyun #define RK3399_CABC_CTRL1 0x01c4 589*4882a593Smuzhiyun #define RK3399_CABC_CTRL2 0x01c8 590*4882a593Smuzhiyun #define RK3399_CABC_CTRL3 0x01cc 591*4882a593Smuzhiyun #define RK3399_CABC_GAUSS_LINE0_0 0x01d0 592*4882a593Smuzhiyun #define RK3399_CABC_GAUSS_LINE0_1 0x01d4 593*4882a593Smuzhiyun #define RK3399_CABC_GAUSS_LINE1_0 0x01d8 594*4882a593Smuzhiyun #define RK3399_CABC_GAUSS_LINE1_1 0x01dc 595*4882a593Smuzhiyun #define RK3399_CABC_GAUSS_LINE2_0 0x01e0 596*4882a593Smuzhiyun #define RK3399_CABC_GAUSS_LINE2_1 0x01e4 597*4882a593Smuzhiyun #define RK3399_FRC_LOWER01_0 0x01e8 598*4882a593Smuzhiyun #define RK3399_FRC_LOWER01_1 0x01ec 599*4882a593Smuzhiyun #define RK3399_FRC_LOWER10_0 0x01f0 600*4882a593Smuzhiyun #define RK3399_FRC_LOWER10_1 0x01f4 601*4882a593Smuzhiyun #define RK3399_FRC_LOWER11_0 0x01f8 602*4882a593Smuzhiyun #define RK3399_FRC_LOWER11_1 0x01fc 603*4882a593Smuzhiyun #define RK3399_AFBCD0_CTRL 0x0200 604*4882a593Smuzhiyun #define RK3399_AFBCD0_HDR_PTR 0x0204 605*4882a593Smuzhiyun #define RK3399_AFBCD0_PIC_SIZE 0x0208 606*4882a593Smuzhiyun #define RK3399_AFBCD0_STATUS 0x020c 607*4882a593Smuzhiyun #define RK3399_AFBCD1_CTRL 0x0220 608*4882a593Smuzhiyun #define RK3399_AFBCD1_HDR_PTR 0x0224 609*4882a593Smuzhiyun #define RK3399_AFBCD1_PIC_SIZE 0x0228 610*4882a593Smuzhiyun #define RK3399_AFBCD1_STATUS 0x022c 611*4882a593Smuzhiyun #define RK3399_AFBCD2_CTRL 0x0240 612*4882a593Smuzhiyun #define RK3399_AFBCD2_HDR_PTR 0x0244 613*4882a593Smuzhiyun #define RK3399_AFBCD2_PIC_SIZE 0x0248 614*4882a593Smuzhiyun #define RK3399_AFBCD2_STATUS 0x024c 615*4882a593Smuzhiyun #define RK3399_AFBCD3_CTRL 0x0260 616*4882a593Smuzhiyun #define RK3399_AFBCD3_HDR_PTR 0x0264 617*4882a593Smuzhiyun #define RK3399_AFBCD3_PIC_SIZE 0x0268 618*4882a593Smuzhiyun #define RK3399_AFBCD3_STATUS 0x026c 619*4882a593Smuzhiyun #define RK3399_INTR_EN0 0x0280 620*4882a593Smuzhiyun #define RK3399_INTR_CLEAR0 0x0284 621*4882a593Smuzhiyun #define RK3399_INTR_STATUS0 0x0288 622*4882a593Smuzhiyun #define RK3399_INTR_RAW_STATUS0 0x028c 623*4882a593Smuzhiyun #define RK3399_INTR_EN1 0x0290 624*4882a593Smuzhiyun #define RK3399_INTR_CLEAR1 0x0294 625*4882a593Smuzhiyun #define RK3399_INTR_STATUS1 0x0298 626*4882a593Smuzhiyun #define RK3399_INTR_RAW_STATUS1 0x029c 627*4882a593Smuzhiyun #define RK3399_LINE_FLAG 0x02a0 628*4882a593Smuzhiyun #define RK3399_VOP_STATUS 0x02a4 629*4882a593Smuzhiyun #define RK3399_BLANKING_VALUE 0x02a8 630*4882a593Smuzhiyun #define RK3399_MCU_BYPASS_PORT 0x02ac 631*4882a593Smuzhiyun #define RK3399_WIN0_DSP_BG 0x02b0 632*4882a593Smuzhiyun #define RK3399_WIN1_DSP_BG 0x02b4 633*4882a593Smuzhiyun #define RK3399_WIN2_DSP_BG 0x02b8 634*4882a593Smuzhiyun #define RK3399_WIN3_DSP_BG 0x02bc 635*4882a593Smuzhiyun #define RK3399_YUV2YUV_WIN 0x02c0 636*4882a593Smuzhiyun #define RK3399_YUV2YUV_POST 0x02c4 637*4882a593Smuzhiyun #define RK3399_AUTO_GATING_EN 0x02cc 638*4882a593Smuzhiyun #define RK3399_WIN0_CSC_COE 0x03a0 639*4882a593Smuzhiyun #define RK3399_WIN1_CSC_COE 0x03c0 640*4882a593Smuzhiyun #define RK3399_WIN2_CSC_COE 0x03e0 641*4882a593Smuzhiyun #define RK3399_WIN3_CSC_COE 0x0400 642*4882a593Smuzhiyun #define RK3399_HWC_CSC_COE 0x0420 643*4882a593Smuzhiyun #define RK3399_BCSH_R2Y_CSC_COE 0x0440 644*4882a593Smuzhiyun #define RK3399_BCSH_Y2R_CSC_COE 0x0460 645*4882a593Smuzhiyun #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 646*4882a593Smuzhiyun #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 647*4882a593Smuzhiyun #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 648*4882a593Smuzhiyun #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 649*4882a593Smuzhiyun #define RK3399_WIN0_YUV2YUV_3X3 0x0500 650*4882a593Smuzhiyun #define RK3399_WIN0_YUV2YUV_R2Y 0x0520 651*4882a593Smuzhiyun #define RK3399_WIN1_YUV2YUV_Y2R 0x0540 652*4882a593Smuzhiyun #define RK3399_WIN1_YUV2YUV_3X3 0x0560 653*4882a593Smuzhiyun #define RK3399_WIN1_YUV2YUV_R2Y 0x0580 654*4882a593Smuzhiyun #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 655*4882a593Smuzhiyun #define RK3399_WIN2_YUV2YUV_3X3 0x05c0 656*4882a593Smuzhiyun #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 657*4882a593Smuzhiyun #define RK3399_WIN3_YUV2YUV_Y2R 0x0600 658*4882a593Smuzhiyun #define RK3399_WIN3_YUV2YUV_3X3 0x0620 659*4882a593Smuzhiyun #define RK3399_WIN3_YUV2YUV_R2Y 0x0640 660*4882a593Smuzhiyun #define RK3399_WIN2_LUT_ADDR 0x1000 661*4882a593Smuzhiyun #define RK3399_WIN3_LUT_ADDR 0x1400 662*4882a593Smuzhiyun #define RK3399_HWC_LUT_ADDR 0x1800 663*4882a593Smuzhiyun #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 664*4882a593Smuzhiyun #define RK3399_GAMMA_LUT_ADDR 0x2000 665*4882a593Smuzhiyun /* rk3399 register definition end */ 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun /* rk3328 register definition end */ 668*4882a593Smuzhiyun #define RK3328_REG_CFG_DONE 0x00000000 669*4882a593Smuzhiyun #define RK3328_VERSION_INFO 0x00000004 670*4882a593Smuzhiyun #define RK3328_SYS_CTRL 0x00000008 671*4882a593Smuzhiyun #define RK3328_SYS_CTRL1 0x0000000c 672*4882a593Smuzhiyun #define RK3328_DSP_CTRL0 0x00000010 673*4882a593Smuzhiyun #define RK3328_DSP_CTRL1 0x00000014 674*4882a593Smuzhiyun #define RK3328_DSP_BG 0x00000018 675*4882a593Smuzhiyun #define RK3328_AUTO_GATING_EN 0x0000003c 676*4882a593Smuzhiyun #define RK3328_LINE_FLAG 0x00000040 677*4882a593Smuzhiyun #define RK3328_VOP_STATUS 0x00000044 678*4882a593Smuzhiyun #define RK3328_BLANKING_VALUE 0x00000048 679*4882a593Smuzhiyun #define RK3328_WIN0_DSP_BG 0x00000050 680*4882a593Smuzhiyun #define RK3328_WIN1_DSP_BG 0x00000054 681*4882a593Smuzhiyun #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 682*4882a593Smuzhiyun #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 683*4882a593Smuzhiyun #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 684*4882a593Smuzhiyun #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc 685*4882a593Smuzhiyun #define RK3328_INTR_EN0 0x000000e0 686*4882a593Smuzhiyun #define RK3328_INTR_CLEAR0 0x000000e4 687*4882a593Smuzhiyun #define RK3328_INTR_STATUS0 0x000000e8 688*4882a593Smuzhiyun #define RK3328_INTR_RAW_STATUS0 0x000000ec 689*4882a593Smuzhiyun #define RK3328_INTR_EN1 0x000000f0 690*4882a593Smuzhiyun #define RK3328_INTR_CLEAR1 0x000000f4 691*4882a593Smuzhiyun #define RK3328_INTR_STATUS1 0x000000f8 692*4882a593Smuzhiyun #define RK3328_INTR_RAW_STATUS1 0x000000fc 693*4882a593Smuzhiyun #define RK3328_WIN0_CTRL0 0x00000100 694*4882a593Smuzhiyun #define RK3328_WIN0_CTRL1 0x00000104 695*4882a593Smuzhiyun #define RK3328_WIN0_COLOR_KEY 0x00000108 696*4882a593Smuzhiyun #define RK3328_WIN0_VIR 0x0000010c 697*4882a593Smuzhiyun #define RK3328_WIN0_YRGB_MST 0x00000110 698*4882a593Smuzhiyun #define RK3328_WIN0_CBR_MST 0x00000114 699*4882a593Smuzhiyun #define RK3328_WIN0_ACT_INFO 0x00000118 700*4882a593Smuzhiyun #define RK3328_WIN0_DSP_INFO 0x0000011c 701*4882a593Smuzhiyun #define RK3328_WIN0_DSP_ST 0x00000120 702*4882a593Smuzhiyun #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 703*4882a593Smuzhiyun #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 704*4882a593Smuzhiyun #define RK3328_WIN0_SCL_OFFSET 0x0000012c 705*4882a593Smuzhiyun #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 706*4882a593Smuzhiyun #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 707*4882a593Smuzhiyun #define RK3328_WIN0_FADING_CTRL 0x00000138 708*4882a593Smuzhiyun #define RK3328_WIN0_CTRL2 0x0000013c 709*4882a593Smuzhiyun #define RK3328_DBG_WIN0_REG0 0x000001f0 710*4882a593Smuzhiyun #define RK3328_DBG_WIN0_REG1 0x000001f4 711*4882a593Smuzhiyun #define RK3328_DBG_WIN0_REG2 0x000001f8 712*4882a593Smuzhiyun #define RK3328_DBG_WIN0_RESERVED 0x000001fc 713*4882a593Smuzhiyun #define RK3328_WIN1_CTRL0 0x00000200 714*4882a593Smuzhiyun #define RK3328_WIN1_CTRL1 0x00000204 715*4882a593Smuzhiyun #define RK3328_WIN1_COLOR_KEY 0x00000208 716*4882a593Smuzhiyun #define RK3328_WIN1_VIR 0x0000020c 717*4882a593Smuzhiyun #define RK3328_WIN1_YRGB_MST 0x00000210 718*4882a593Smuzhiyun #define RK3328_WIN1_CBR_MST 0x00000214 719*4882a593Smuzhiyun #define RK3328_WIN1_ACT_INFO 0x00000218 720*4882a593Smuzhiyun #define RK3328_WIN1_DSP_INFO 0x0000021c 721*4882a593Smuzhiyun #define RK3328_WIN1_DSP_ST 0x00000220 722*4882a593Smuzhiyun #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 723*4882a593Smuzhiyun #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 724*4882a593Smuzhiyun #define RK3328_WIN1_SCL_OFFSET 0x0000022c 725*4882a593Smuzhiyun #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 726*4882a593Smuzhiyun #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 727*4882a593Smuzhiyun #define RK3328_WIN1_FADING_CTRL 0x00000238 728*4882a593Smuzhiyun #define RK3328_WIN1_CTRL2 0x0000023c 729*4882a593Smuzhiyun #define RK3328_DBG_WIN1_REG0 0x000002f0 730*4882a593Smuzhiyun #define RK3328_DBG_WIN1_REG1 0x000002f4 731*4882a593Smuzhiyun #define RK3328_DBG_WIN1_REG2 0x000002f8 732*4882a593Smuzhiyun #define RK3328_DBG_WIN1_RESERVED 0x000002fc 733*4882a593Smuzhiyun #define RK3328_WIN2_CTRL0 0x00000300 734*4882a593Smuzhiyun #define RK3328_WIN2_CTRL1 0x00000304 735*4882a593Smuzhiyun #define RK3328_WIN2_COLOR_KEY 0x00000308 736*4882a593Smuzhiyun #define RK3328_WIN2_VIR 0x0000030c 737*4882a593Smuzhiyun #define RK3328_WIN2_YRGB_MST 0x00000310 738*4882a593Smuzhiyun #define RK3328_WIN2_CBR_MST 0x00000314 739*4882a593Smuzhiyun #define RK3328_WIN2_ACT_INFO 0x00000318 740*4882a593Smuzhiyun #define RK3328_WIN2_DSP_INFO 0x0000031c 741*4882a593Smuzhiyun #define RK3328_WIN2_DSP_ST 0x00000320 742*4882a593Smuzhiyun #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 743*4882a593Smuzhiyun #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 744*4882a593Smuzhiyun #define RK3328_WIN2_SCL_OFFSET 0x0000032c 745*4882a593Smuzhiyun #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 746*4882a593Smuzhiyun #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 747*4882a593Smuzhiyun #define RK3328_WIN2_FADING_CTRL 0x00000338 748*4882a593Smuzhiyun #define RK3328_WIN2_CTRL2 0x0000033c 749*4882a593Smuzhiyun #define RK3328_DBG_WIN2_REG0 0x000003f0 750*4882a593Smuzhiyun #define RK3328_DBG_WIN2_REG1 0x000003f4 751*4882a593Smuzhiyun #define RK3328_DBG_WIN2_REG2 0x000003f8 752*4882a593Smuzhiyun #define RK3328_DBG_WIN2_RESERVED 0x000003fc 753*4882a593Smuzhiyun #define RK3328_WIN3_CTRL0 0x00000400 754*4882a593Smuzhiyun #define RK3328_WIN3_CTRL1 0x00000404 755*4882a593Smuzhiyun #define RK3328_WIN3_COLOR_KEY 0x00000408 756*4882a593Smuzhiyun #define RK3328_WIN3_VIR 0x0000040c 757*4882a593Smuzhiyun #define RK3328_WIN3_YRGB_MST 0x00000410 758*4882a593Smuzhiyun #define RK3328_WIN3_CBR_MST 0x00000414 759*4882a593Smuzhiyun #define RK3328_WIN3_ACT_INFO 0x00000418 760*4882a593Smuzhiyun #define RK3328_WIN3_DSP_INFO 0x0000041c 761*4882a593Smuzhiyun #define RK3328_WIN3_DSP_ST 0x00000420 762*4882a593Smuzhiyun #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 763*4882a593Smuzhiyun #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 764*4882a593Smuzhiyun #define RK3328_WIN3_SCL_OFFSET 0x0000042c 765*4882a593Smuzhiyun #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 766*4882a593Smuzhiyun #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 767*4882a593Smuzhiyun #define RK3328_WIN3_FADING_CTRL 0x00000438 768*4882a593Smuzhiyun #define RK3328_WIN3_CTRL2 0x0000043c 769*4882a593Smuzhiyun #define RK3328_DBG_WIN3_REG0 0x000004f0 770*4882a593Smuzhiyun #define RK3328_DBG_WIN3_REG1 0x000004f4 771*4882a593Smuzhiyun #define RK3328_DBG_WIN3_REG2 0x000004f8 772*4882a593Smuzhiyun #define RK3328_DBG_WIN3_RESERVED 0x000004fc 773*4882a593Smuzhiyun 774*4882a593Smuzhiyun #define RK3328_HWC_CTRL0 0x00000500 775*4882a593Smuzhiyun #define RK3328_HWC_CTRL1 0x00000504 776*4882a593Smuzhiyun #define RK3328_HWC_MST 0x00000508 777*4882a593Smuzhiyun #define RK3328_HWC_DSP_ST 0x0000050c 778*4882a593Smuzhiyun #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 779*4882a593Smuzhiyun #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 780*4882a593Smuzhiyun #define RK3328_HWC_FADING_CTRL 0x00000518 781*4882a593Smuzhiyun #define RK3328_HWC_RESERVED1 0x0000051c 782*4882a593Smuzhiyun #define RK3328_POST_DSP_HACT_INFO 0x00000600 783*4882a593Smuzhiyun #define RK3328_POST_DSP_VACT_INFO 0x00000604 784*4882a593Smuzhiyun #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 785*4882a593Smuzhiyun #define RK3328_POST_RESERVED 0x0000060c 786*4882a593Smuzhiyun #define RK3328_POST_SCL_CTRL 0x00000610 787*4882a593Smuzhiyun #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 788*4882a593Smuzhiyun #define RK3328_DSP_HTOTAL_HS_END 0x00000618 789*4882a593Smuzhiyun #define RK3328_DSP_HACT_ST_END 0x0000061c 790*4882a593Smuzhiyun #define RK3328_DSP_VTOTAL_VS_END 0x00000620 791*4882a593Smuzhiyun #define RK3328_DSP_VACT_ST_END 0x00000624 792*4882a593Smuzhiyun #define RK3328_DSP_VS_ST_END_F1 0x00000628 793*4882a593Smuzhiyun #define RK3328_DSP_VACT_ST_END_F1 0x0000062c 794*4882a593Smuzhiyun #define RK3328_BCSH_COLOR_BAR 0x00000640 795*4882a593Smuzhiyun #define RK3328_BCSH_BCS 0x00000644 796*4882a593Smuzhiyun #define RK3328_BCSH_H 0x00000648 797*4882a593Smuzhiyun #define RK3328_BCSH_CTRL 0x0000064c 798*4882a593Smuzhiyun #define RK3328_FRC_LOWER01_0 0x00000678 799*4882a593Smuzhiyun #define RK3328_FRC_LOWER01_1 0x0000067c 800*4882a593Smuzhiyun #define RK3328_FRC_LOWER10_0 0x00000680 801*4882a593Smuzhiyun #define RK3328_FRC_LOWER10_1 0x00000684 802*4882a593Smuzhiyun #define RK3328_FRC_LOWER11_0 0x00000688 803*4882a593Smuzhiyun #define RK3328_FRC_LOWER11_1 0x0000068c 804*4882a593Smuzhiyun #define RK3328_DBG_POST_REG0 0x000006e8 805*4882a593Smuzhiyun #define RK3328_DBG_POST_RESERVED 0x000006ec 806*4882a593Smuzhiyun #define RK3328_DBG_DATAO 0x000006f0 807*4882a593Smuzhiyun #define RK3328_DBG_DATAO_2 0x000006f4 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun /* sdr to hdr */ 810*4882a593Smuzhiyun #define RK3328_SDR2HDR_CTRL 0x00000700 811*4882a593Smuzhiyun #define RK3328_EOTF_OETF_Y0 0x00000704 812*4882a593Smuzhiyun #define RK3328_RESERVED0001 0x00000708 813*4882a593Smuzhiyun #define RK3328_RESERVED0002 0x0000070c 814*4882a593Smuzhiyun #define RK3328_EOTF_OETF_Y1 0x00000710 815*4882a593Smuzhiyun #define RK3328_EOTF_OETF_Y64 0x0000080c 816*4882a593Smuzhiyun #define RK3328_OETF_DX_DXPOW1 0x00000810 817*4882a593Smuzhiyun #define RK3328_OETF_DX_DXPOW64 0x0000090c 818*4882a593Smuzhiyun #define RK3328_OETF_XN1 0x00000910 819*4882a593Smuzhiyun #define RK3328_OETF_XN63 0x00000a08 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun /* hdr to sdr */ 822*4882a593Smuzhiyun #define RK3328_HDR2SDR_CTRL 0x00000a10 823*4882a593Smuzhiyun #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 824*4882a593Smuzhiyun #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 825*4882a593Smuzhiyun #define RK3328_RESERVED0003 0x00000a1c 826*4882a593Smuzhiyun #define RK3328_HDR2SDR_DST_RANGE 0x00000a20 827*4882a593Smuzhiyun #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 828*4882a593Smuzhiyun #define RK3328_EETF_OETF_Y0 0x00000a28 829*4882a593Smuzhiyun #define RK3328_SAT_Y0 0x00000a2c 830*4882a593Smuzhiyun #define RK3328_EETF_OETF_Y1 0x00000a30 831*4882a593Smuzhiyun #define RK3328_SAT_Y1 0x00000ab0 832*4882a593Smuzhiyun #define RK3328_SAT_Y8 0x00000acc 833*4882a593Smuzhiyun 834*4882a593Smuzhiyun #define RK3328_HWC_LUT_ADDR 0x00000c00 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun /* rk3036 register definition */ 837*4882a593Smuzhiyun #define RK3036_SYS_CTRL 0x00 838*4882a593Smuzhiyun #define RK3036_DSP_CTRL0 0x04 839*4882a593Smuzhiyun #define RK3036_DSP_CTRL1 0x08 840*4882a593Smuzhiyun #define RK3036_INT_SCALER 0x0c 841*4882a593Smuzhiyun #define RK3036_INT_STATUS 0x10 842*4882a593Smuzhiyun #define RK3036_ALPHA_CTRL 0x14 843*4882a593Smuzhiyun #define RK3036_WIN0_COLOR_KEY 0x18 844*4882a593Smuzhiyun #define RK3036_WIN1_COLOR_KEY 0x1c 845*4882a593Smuzhiyun #define RK3036_WIN0_YRGB_MST 0x20 846*4882a593Smuzhiyun #define RK3036_WIN0_CBR_MST 0x24 847*4882a593Smuzhiyun #define RK3036_WIN1_VIR 0x28 848*4882a593Smuzhiyun #define RK3036_AXI_BUS_CTRL 0x2c 849*4882a593Smuzhiyun #define RK3036_WIN0_VIR 0x30 850*4882a593Smuzhiyun #define RK3036_WIN0_ACT_INFO 0x34 851*4882a593Smuzhiyun #define RK3036_WIN0_DSP_INFO 0x38 852*4882a593Smuzhiyun #define RK3036_WIN0_DSP_ST 0x3c 853*4882a593Smuzhiyun #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 854*4882a593Smuzhiyun #define RK3036_WIN0_SCL_FACTOR_CBR 0x44 855*4882a593Smuzhiyun #define RK3036_WIN0_SCL_OFFSET 0x48 856*4882a593Smuzhiyun #define RK3036_HWC_MST 0x58 857*4882a593Smuzhiyun #define RK3036_HWC_DSP_ST 0x5c 858*4882a593Smuzhiyun #define RK3036_DSP_HTOTAL_HS_END 0x6c 859*4882a593Smuzhiyun #define RK3036_DSP_HACT_ST_END 0x70 860*4882a593Smuzhiyun #define RK3036_DSP_VTOTAL_VS_END 0x74 861*4882a593Smuzhiyun #define RK3036_DSP_VACT_ST_END 0x78 862*4882a593Smuzhiyun #define RK3036_DSP_VS_ST_END_F1 0x7c 863*4882a593Smuzhiyun #define RK3036_DSP_VACT_ST_END_F1 0x80 864*4882a593Smuzhiyun #define RK3036_GATHER_TRANSFER 0x84 865*4882a593Smuzhiyun #define RK3036_VERSION_INFO 0x94 866*4882a593Smuzhiyun #define RK3036_REG_CFG_DONE 0x90 867*4882a593Smuzhiyun #define RK3036_WIN1_MST 0xa0 868*4882a593Smuzhiyun #define RK3036_WIN1_ACT_INFO 0xb4 869*4882a593Smuzhiyun #define RK3036_WIN1_DSP_INFO 0xb8 870*4882a593Smuzhiyun #define RK3036_WIN1_DSP_ST 0xbc 871*4882a593Smuzhiyun #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 872*4882a593Smuzhiyun #define RK3036_WIN1_SCL_OFFSET 0xc8 873*4882a593Smuzhiyun #define RK3036_BCSH_CTRL 0xd0 874*4882a593Smuzhiyun #define RK3036_BCSH_COLOR_BAR 0xd4 875*4882a593Smuzhiyun #define RK3036_BCSH_BCS 0xd8 876*4882a593Smuzhiyun #define RK3036_BCSH_H 0xdc 877*4882a593Smuzhiyun #define RK3036_WIN1_LUT_ADDR 0x400 878*4882a593Smuzhiyun #define RK3036_HWC_LUT_ADDR 0x800 879*4882a593Smuzhiyun /* rk3036 register definition end */ 880*4882a593Smuzhiyun 881*4882a593Smuzhiyun /* rk3126 register definition */ 882*4882a593Smuzhiyun #define RK3126_WIN1_MST 0x0004c 883*4882a593Smuzhiyun #define RK3126_WIN1_DSP_INFO 0x00050 884*4882a593Smuzhiyun #define RK3126_WIN1_DSP_ST 0x00054 885*4882a593Smuzhiyun /* rk3126 register definition end */ 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun /* rk3366 register definition */ 888*4882a593Smuzhiyun #define RK3366_LIT_REG_CFG_DONE 0x00000 889*4882a593Smuzhiyun #define RK3366_LIT_VERSION 0x00004 890*4882a593Smuzhiyun #define RK3366_LIT_DSP_BG 0x00008 891*4882a593Smuzhiyun #define RK3366_LIT_MCU_CTRL 0x0000c 892*4882a593Smuzhiyun #define RK3366_LIT_SYS_CTRL0 0x00010 893*4882a593Smuzhiyun #define RK3366_LIT_SYS_CTRL1 0x00014 894*4882a593Smuzhiyun #define RK3366_LIT_SYS_CTRL2 0x00018 895*4882a593Smuzhiyun #define RK3366_LIT_DSP_CTRL0 0x00020 896*4882a593Smuzhiyun #define RK3366_LIT_DSP_CTRL2 0x00028 897*4882a593Smuzhiyun #define RK3366_LIT_VOP_STATUS 0x0002c 898*4882a593Smuzhiyun #define RK3366_LIT_LINE_FLAG 0x00030 899*4882a593Smuzhiyun #define RK3366_LIT_INTR_EN 0x00034 900*4882a593Smuzhiyun #define RK3366_LIT_INTR_CLEAR 0x00038 901*4882a593Smuzhiyun #define RK3366_LIT_INTR_STATUS 0x0003c 902*4882a593Smuzhiyun #define RK3366_LIT_WIN0_CTRL0 0x00050 903*4882a593Smuzhiyun #define RK3366_LIT_WIN0_CTRL1 0x00054 904*4882a593Smuzhiyun #define RK3366_LIT_WIN0_COLOR_KEY 0x00058 905*4882a593Smuzhiyun #define RK3366_LIT_WIN0_VIR 0x0005c 906*4882a593Smuzhiyun #define RK3366_LIT_WIN0_YRGB_MST0 0x00060 907*4882a593Smuzhiyun #define RK3366_LIT_WIN0_CBR_MST0 0x00064 908*4882a593Smuzhiyun #define RK3366_LIT_WIN0_ACT_INFO 0x00068 909*4882a593Smuzhiyun #define RK3366_LIT_WIN0_DSP_INFO 0x0006c 910*4882a593Smuzhiyun #define RK3366_LIT_WIN0_DSP_ST 0x00070 911*4882a593Smuzhiyun #define RK3366_LIT_WIN0_SCL_FACTOR_YRGB 0x00074 912*4882a593Smuzhiyun #define RK3366_LIT_WIN0_SCL_FACTOR_CBR 0x00078 913*4882a593Smuzhiyun #define RK3366_LIT_WIN0_SCL_OFFSET 0x0007c 914*4882a593Smuzhiyun #define RK3366_LIT_WIN0_ALPHA_CTRL 0x00080 915*4882a593Smuzhiyun #define RK3366_LIT_WIN1_CTRL0 0x00090 916*4882a593Smuzhiyun #define RK3366_LIT_WIN1_CTRL1 0x00094 917*4882a593Smuzhiyun #define RK3366_LIT_WIN1_VIR 0x00098 918*4882a593Smuzhiyun #define RK3366_LIT_WIN1_MST 0x000a0 919*4882a593Smuzhiyun #define RK3366_LIT_WIN1_DSP_INFO 0x000a4 920*4882a593Smuzhiyun #define RK3366_LIT_WIN1_DSP_ST 0x000a8 921*4882a593Smuzhiyun #define RK3366_LIT_WIN1_COLOR_KEY 0x000ac 922*4882a593Smuzhiyun #define RK3366_LIT_WIN1_ALPHA_CTRL 0x000bc 923*4882a593Smuzhiyun #define RK3366_LIT_HWC_CTRL0 0x000e0 924*4882a593Smuzhiyun #define RK3366_LIT_HWC_CTRL1 0x000e4 925*4882a593Smuzhiyun #define RK3366_LIT_HWC_MST 0x000e8 926*4882a593Smuzhiyun #define RK3366_LIT_HWC_DSP_ST 0x000ec 927*4882a593Smuzhiyun #define RK3366_LIT_HWC_ALPHA_CTRL 0x000f0 928*4882a593Smuzhiyun #define RK3366_LIT_DSP_HTOTAL_HS_END 0x00100 929*4882a593Smuzhiyun #define RK3366_LIT_DSP_HACT_ST_END 0x00104 930*4882a593Smuzhiyun #define RK3366_LIT_DSP_VTOTAL_VS_END 0x00108 931*4882a593Smuzhiyun #define RK3366_LIT_DSP_VACT_ST_END 0x0010c 932*4882a593Smuzhiyun #define RK3366_LIT_DSP_VS_ST_END_F1 0x00110 933*4882a593Smuzhiyun #define RK3366_LIT_DSP_VACT_ST_END_F1 0x00114 934*4882a593Smuzhiyun #define RK3366_LIT_BCSH_CTRL 0x00160 935*4882a593Smuzhiyun #define RK3366_LIT_BCSH_COL_BAR 0x00164 936*4882a593Smuzhiyun #define RK3366_LIT_BCSH_BCS 0x00168 937*4882a593Smuzhiyun #define RK3366_LIT_BCSH_H 0x0016c 938*4882a593Smuzhiyun #define RK3366_LIT_FRC_LOWER01_0 0x00170 939*4882a593Smuzhiyun #define RK3366_LIT_FRC_LOWER01_1 0x00174 940*4882a593Smuzhiyun #define RK3366_LIT_FRC_LOWER10_0 0x00178 941*4882a593Smuzhiyun #define RK3366_LIT_FRC_LOWER10_1 0x0017c 942*4882a593Smuzhiyun #define RK3366_LIT_FRC_LOWER11_0 0x00180 943*4882a593Smuzhiyun #define RK3366_LIT_FRC_LOWER11_1 0x00184 944*4882a593Smuzhiyun #define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c 945*4882a593Smuzhiyun #define RK3366_LIT_DBG_REG_000 0x00190 946*4882a593Smuzhiyun #define RK3366_LIT_BLANKING_VALUE 0x001f4 947*4882a593Smuzhiyun #define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8 948*4882a593Smuzhiyun #define RK3366_LIT_FLAG_REG 0x001fc 949*4882a593Smuzhiyun #define RK3366_LIT_HWC_LUT_ADDR 0x00600 950*4882a593Smuzhiyun #define RK3366_LIT_GAMMA_LUT_ADDR 0x00a00 951*4882a593Smuzhiyun /* rk3366 register definition end */ 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun /* px30 register definition */ 954*4882a593Smuzhiyun #define PX30_CABC_CTRL0 0x00200 955*4882a593Smuzhiyun #define PX30_CABC_CTRL1 0x00204 956*4882a593Smuzhiyun #define PX30_CABC_CTRL2 0x00208 957*4882a593Smuzhiyun #define PX30_CABC_CTRL3 0x0020c 958*4882a593Smuzhiyun #define PX30_CABC_GAUSS_LINE0_0 0x00210 959*4882a593Smuzhiyun #define PX30_CABC_GAUSS_LINE0_1 0x00214 960*4882a593Smuzhiyun #define PX30_CABC_GAUSS_LINE1_0 0x00218 961*4882a593Smuzhiyun #define PX30_CABC_GAUSS_LINE1_1 0x0021c 962*4882a593Smuzhiyun #define PX30_CABC_GAUSS_LINE2_0 0x00220 963*4882a593Smuzhiyun #define PX30_CABC_GAUSS_LINE2_1 0x00224 964*4882a593Smuzhiyun #define PX30_AFBCD0_CTRL 0x00240 965*4882a593Smuzhiyun #define PX30_AFBCD0_HDR_PTR 0x00244 966*4882a593Smuzhiyun #define PX30_AFBCD0_PIC_SIZE 0x00248 967*4882a593Smuzhiyun #define PX30_AFBCD0_PIC_OFFSET 0x0024c 968*4882a593Smuzhiyun #define PX30_AFBCD0_AXI_CTRL 0x00250 969*4882a593Smuzhiyun #define PX30_GRF_PD_VO_CON1 0x00438 970*4882a593Smuzhiyun /* px30 register definition end */ 971*4882a593Smuzhiyun 972*4882a593Smuzhiyun /* rk1808 register definition start*/ 973*4882a593Smuzhiyun #define RK1808_GRF_PD_VO_CON1 0x00000444 974*4882a593Smuzhiyun /* rk1808 register definition end*/ 975*4882a593Smuzhiyun 976*4882a593Smuzhiyun /* RV1126 register definition start */ 977*4882a593Smuzhiyun #define RV1126_WIN2_CTRL0 0x0190 978*4882a593Smuzhiyun #define RV1126_WIN2_VIR0_1 0x0198 979*4882a593Smuzhiyun #define RV1126_WIN2_MST0 0x01a0 980*4882a593Smuzhiyun #define RV1126_WIN2_DSP_INFO0 0x01a4 981*4882a593Smuzhiyun #define RV1126_WIN2_DSP_ST0 0x01a8 982*4882a593Smuzhiyun /* RV1126 register definition end */ 983*4882a593Smuzhiyun #endif /* _ROCKCHIP_VOP_REG_H */ 984