1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .reg_done_frm = VOP_REG_VER(RK3288_SYS_CTRL1, 0x1, 24, 3, 7, -1), 92 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 93 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 94 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 95 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 96 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 97 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 98 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 100 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 101 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 102 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 103 104 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 105 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 106 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 107 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 108 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 109 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 110 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 111 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 112 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 113 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 114 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 115 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 116 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 117 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 118 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 119 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 120 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1), 121 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 122 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1), 123 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1), 124 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1), 125 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1), 126 .tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24), 127 .tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25), 128 .tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26), 129 .sw_uv_offset_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 27), 130 .sw_genlock = VOP_REG(RK3288_SYS_CTRL, 0x1, 28), 131 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1), 132 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1), 133 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1), 134 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1), 135 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1), 136 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1), 137 138 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 139 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 140 141 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 142 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 143 .dsp_bg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 12), 144 .dsp_rb_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 13), 145 .dsp_rg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 14), 146 .dsp_delta_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 15), 147 .dsp_dummy_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 16), 148 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 149 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 150 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 151 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 152 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 153 154 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 155 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 156 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 157 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 158 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 159 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 160 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 161 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 162 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 163 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 164 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 165 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 166 167 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 168 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 169 170 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 171 172 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 173 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 174 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 175 176 .mcu_pix_total = VOP_REG(RK3288_MCU_CTRL, 0x3f, 0), 177 .mcu_cs_pst = VOP_REG(RK3288_MCU_CTRL, 0xf, 6), 178 .mcu_cs_pend = VOP_REG(RK3288_MCU_CTRL, 0x3f, 10), 179 .mcu_rw_pst = VOP_REG(RK3288_MCU_CTRL, 0xf, 16), 180 .mcu_rw_pend = VOP_REG(RK3288_MCU_CTRL, 0x3f, 20), 181 .mcu_clk_sel = VOP_REG(RK3288_MCU_CTRL, 0x1, 26), 182 .mcu_hold_mode = VOP_REG(RK3288_MCU_CTRL, 0x1, 27), 183 .mcu_frame_st = VOP_REG(RK3288_MCU_CTRL, 0x1, 28), 184 .mcu_rs = VOP_REG(RK3288_MCU_CTRL, 0x1, 29), 185 .mcu_bypass = VOP_REG(RK3288_MCU_CTRL, 0x1, 30), 186 .mcu_type = VOP_REG(RK3288_MCU_CTRL, 0x1, 31), 187 .mcu_rw_bypass_port = VOP_REG(RK3288_MCU_BYPASS_WPORT, 0xffffffff, 0), 188 }; 189 190 static const struct vop_line_flag rk3288_vop_line_flag = { 191 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 192 }; 193 194 static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = { 195 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 13), 196 }; 197 198 static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = { 199 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 15), 200 }; 201 202 const struct vop_data rk3288_vop_big = { 203 .version = VOP_VERSION(3, 1), 204 .max_output = {3840, 2160}, 205 .feature = VOP_FEATURE_OUTPUT_10BIT, 206 .ctrl = &rk3288_ctrl_data, 207 .grf_ctrl = &rk3288_vop_big_grf_ctrl, 208 .win = &rk3288_win01_data, 209 .line_flag = &rk3288_vop_line_flag, 210 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 211 }; 212 213 const struct vop_data rk3288_vop_lit = { 214 .version = VOP_VERSION(3, 1), 215 .max_output = {2560, 1600}, 216 .feature = VOP_FEATURE_OUTPUT_10BIT, 217 .ctrl = &rk3288_ctrl_data, 218 .grf_ctrl = &rk3288_vop_lit_grf_ctrl, 219 .win = &rk3288_win01_data, 220 .line_flag = &rk3288_vop_line_flag, 221 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 222 }; 223 224 static const struct vop_win rk3368_win23_data = { 225 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 226 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 227 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15), 228 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 229 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 230 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 231 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 232 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 233 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xffff, 0), 234 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0), 235 }; 236 237 static const struct vop_line_flag rk3368_vop_line_flag = { 238 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 239 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 240 }; 241 242 static const struct vop_grf_ctrl rk3368_vop_grf_ctrl = { 243 .grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5), 244 }; 245 246 const struct vop_data rk3368_vop = { 247 .version = VOP_VERSION(3, 2), 248 .max_output = {4096, 2160}, 249 .ctrl = &rk3288_ctrl_data, 250 .grf_ctrl = &rk3368_vop_grf_ctrl, 251 .win = &rk3288_win01_data, 252 .line_flag = &rk3368_vop_line_flag, 253 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 254 }; 255 256 static const struct vop_line_flag rk3366_vop_line_flag = { 257 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 258 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 259 }; 260 261 const struct vop_data rk3366_vop = { 262 .version = VOP_VERSION(3, 4), 263 .max_output = {4096, 2160}, 264 .ctrl = &rk3288_ctrl_data, 265 .win = &rk3288_win01_data, 266 .line_flag = &rk3366_vop_line_flag, 267 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 268 }; 269 270 static const uint32_t vop_csc_r2y_bt601[] = { 271 0x02590132, 0xff530075, 0x0200fead, 0xfe530200, 272 0x0000ffad, 0x00000200, 0x00080200, 0x00080200, 273 }; 274 275 static const uint32_t vop_csc_r2y_bt601_12_235[] = { 276 0x02040107, 0xff680064, 0x01c2fed6, 0xfe8701c2, 277 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200, 278 }; 279 280 static const uint32_t vop_csc_r2y_bt709[] = { 281 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2, 282 0x0000ffd7, 0x00010200, 0x00080200, 0x00080200, 283 }; 284 285 static const uint32_t vop_csc_r2y_bt2020[] = { 286 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1, 287 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200, 288 }; 289 290 static const struct vop_csc_table rk3399_csc_table = { 291 .r2y_bt601 = vop_csc_r2y_bt601, 292 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235, 293 .r2y_bt709 = vop_csc_r2y_bt709, 294 .r2y_bt2020 = vop_csc_r2y_bt2020, 295 }; 296 297 static const struct vop_csc rk3399_win0_csc = { 298 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0), 299 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1), 300 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2), 301 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R, 302 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3, 303 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y, 304 }; 305 306 static const struct vop_csc rk3399_win2_csc = { 307 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16), 308 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 18), 309 .r2r_offset = RK3399_WIN2_YUV2YUV_3X3, 310 311 }; 312 313 const struct vop_data rk3399_vop_big = { 314 .version = VOP_VERSION(3, 5), 315 .max_output = {4096, 2160}, 316 .feature = VOP_FEATURE_OUTPUT_10BIT, 317 .ctrl = &rk3288_ctrl_data, 318 .win = &rk3288_win01_data, 319 .line_flag = &rk3366_vop_line_flag, 320 .csc_table = &rk3399_csc_table, 321 .win_csc = &rk3399_win0_csc, 322 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 323 }; 324 325 const struct vop_data rk3399_vop_lit = { 326 .version = VOP_VERSION(3, 6), 327 .max_output = {2560, 1600}, 328 .ctrl = &rk3288_ctrl_data, 329 .win = &rk3368_win23_data, 330 .line_flag = &rk3366_vop_line_flag, 331 .csc_table = &rk3399_csc_table, 332 .win_csc = &rk3399_win2_csc, 333 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 334 }; 335 336 const struct vop_data rk322x_vop = { 337 .version = VOP_VERSION(3, 7), 338 .max_output = {4096, 2160}, 339 .feature = VOP_FEATURE_OUTPUT_10BIT, 340 .ctrl = &rk3288_ctrl_data, 341 .win = &rk3288_win01_data, 342 .line_flag = &rk3366_vop_line_flag, 343 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 344 }; 345 346 static const struct vop_ctrl rk3328_ctrl_data = { 347 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 348 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 349 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 350 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 351 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 352 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 353 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 354 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 355 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 356 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 357 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 358 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 359 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 360 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 361 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 362 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 363 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 364 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 365 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 366 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 367 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 368 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 369 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 370 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 371 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 372 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 373 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 374 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 375 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 376 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 377 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 378 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 379 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 380 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 381 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 382 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 383 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 384 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 385 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 386 387 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 388 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 389 390 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 391 .dsp_bg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 12), 392 .dsp_rb_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 13), 393 .dsp_rg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 14), 394 .dsp_delta_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 15), 395 .dsp_dummy_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 16), 396 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 397 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 398 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 399 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 400 401 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 402 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 403 404 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 405 406 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 407 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 408 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 409 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 410 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 411 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 412 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 413 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 414 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 415 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 416 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 417 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 418 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 419 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 420 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 421 422 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 423 }; 424 425 426 static const struct vop_line_flag rk3328_vop_line_flag = { 427 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 428 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 429 }; 430 431 const struct vop_data rk3328_vop = { 432 .version = VOP_VERSION(3, 8), 433 .max_output = {4096, 2160}, 434 .feature = VOP_FEATURE_OUTPUT_10BIT, 435 .ctrl = &rk3328_ctrl_data, 436 .win = &rk3288_win01_data, 437 .win_offset = 0xd0, 438 .line_flag = &rk3328_vop_line_flag, 439 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 440 }; 441 442 static const struct vop_win rk3126_win1_data = { 443 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 444 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 445 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 446 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0), 447 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), 448 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), 449 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 450 }; 451 452 static const struct vop_ctrl rk3036_ctrl_data = { 453 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 454 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 455 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 456 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7), 457 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 458 .dither_down = VOP_REG(RK3036_DSP_CTRL0, 0x3, 10), 459 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 460 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 461 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 462 .hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22), 463 .hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23), 464 .hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4), 465 .rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24), 466 .rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25), 467 .lvds_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 26), 468 .lvds_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 27), 469 .mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28), 470 .mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29), 471 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 472 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 473 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 474 }; 475 476 static const struct vop_line_flag rk3036_vop_line_flag = { 477 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 478 }; 479 480 const struct vop_data rk3036_vop = { 481 .version = VOP_VERSION(2, 2), 482 .max_output = {1920, 1080}, 483 .ctrl = &rk3036_ctrl_data, 484 .win = &rk3126_win1_data, 485 .line_flag = &rk3036_vop_line_flag, 486 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 487 }; 488 489 static const struct vop_scl_regs rk3366_lit_win_scl = { 490 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 491 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 492 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 493 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 494 }; 495 496 static const struct vop_win rk3366_win0_data = { 497 .scl = &rk3366_lit_win_scl, 498 499 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 500 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 501 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 502 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 503 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 504 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 505 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 506 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 507 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 508 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 509 510 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 511 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 512 }; 513 514 static const struct vop_win rk3366_win1_data = { 515 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 516 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 517 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 518 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 519 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 520 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 521 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 522 523 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 524 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 525 }; 526 527 static const struct vop_ctrl px30_ctrl_data = { 528 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 529 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 530 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 531 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 532 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 533 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 534 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 535 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 536 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 537 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 538 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 539 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 540 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 541 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 542 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 543 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 544 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 545 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 546 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 547 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 548 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 549 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 550 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 551 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 552 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 553 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 554 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 555 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 556 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 557 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9), 558 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11), 559 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12), 560 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 561 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 562 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 563 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 564 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 565 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 566 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 567 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 568 569 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 570 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 571 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 572 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 573 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 574 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 575 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 576 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 577 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 578 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 579 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 580 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 581 582 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 583 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 584 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 585 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 586 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 587 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 588 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 589 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 590 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 591 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 592 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 593 594 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 595 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 596 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 597 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 598 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 599 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 600 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 601 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 602 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 603 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 604 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 605 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 606 0xffffffff, 0), 607 }; 608 609 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 610 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 611 }; 612 613 static const struct vop_grf_ctrl px30_grf_ctrl = { 614 .grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4), 615 }; 616 617 const struct vop_data px30_vop_lit = { 618 .version = VOP_VERSION(2, 5), 619 .max_output = {1920, 1080}, 620 .ctrl = &px30_ctrl_data, 621 .grf_ctrl = &px30_grf_ctrl, 622 .win = &rk3366_win1_data, 623 .line_flag = &rk3366_vop_lite_line_flag, 624 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 625 }; 626 627 const struct vop_data px30_vop_big = { 628 .version = VOP_VERSION(2, 6), 629 .max_output = {1920, 1080}, 630 .ctrl = &px30_ctrl_data, 631 .grf_ctrl = &px30_grf_ctrl, 632 .win = &rk3366_win1_data, 633 .line_flag = &rk3366_vop_lite_line_flag, 634 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 635 }; 636 637 static const struct vop_ctrl rk3308_ctrl_data = { 638 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 639 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 640 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 641 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 642 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 643 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 644 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 645 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 646 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 647 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 648 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 649 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3), 650 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 651 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 652 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 653 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 654 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 655 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 656 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 657 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 658 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9), 659 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11), 660 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12), 661 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 662 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 663 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 664 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 665 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 666 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 667 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 668 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 669 670 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 671 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 672 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 673 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 674 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 675 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 676 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 677 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 678 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 679 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 680 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 681 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 682 683 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 684 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 685 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 686 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 687 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 688 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 689 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 690 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 691 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 692 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 693 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 694 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 695 0xffffffff, 0), 696 }; 697 698 const struct vop_data rk3308_vop = { 699 .version = VOP_VERSION(2, 7), 700 .max_output = {1920, 1080}, 701 .ctrl = &rk3308_ctrl_data, 702 .win = &rk3366_win0_data, 703 .line_flag = &rk3366_vop_lite_line_flag, 704 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 705 }; 706 707 static const struct vop_grf_ctrl rk1808_grf_ctrl = { 708 .grf_dclk_inv = VOP_REG(RK1808_GRF_PD_VO_CON1, 0x1, 4), 709 }; 710 711 const struct vop_data rk1808_vop = { 712 .version = VOP_VERSION(2, 8), 713 .max_output = {1920, 1080}, 714 .ctrl = &px30_ctrl_data, 715 .grf_ctrl = &rk1808_grf_ctrl, 716 .win = &rk3366_win1_data, 717 .line_flag = &rk3366_vop_lite_line_flag, 718 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 719 }; 720 721 const struct vop_data rv1108_vop = { 722 .version = VOP_VERSION(2, 4), 723 .max_output = {1920, 1080}, 724 .ctrl = &rk3308_ctrl_data, 725 .win = &rk3366_win0_data, 726 .line_flag = &rk3366_vop_lite_line_flag, 727 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 728 }; 729 730 static const struct vop_win rv1126_win2_data = { 731 .gate = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 0), 732 .enable = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 4), 733 .format = VOP_REG(RV1126_WIN2_CTRL0, 0x3, 5), 734 .rb_swap = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 20), 735 .dsp_info = VOP_REG(RV1126_WIN2_DSP_INFO0, 0x0fff0fff, 0), 736 .dsp_st = VOP_REG(RV1126_WIN2_DSP_ST0, 0x1fff1fff, 0), 737 .yrgb_mst = VOP_REG(RV1126_WIN2_MST0, 0xffffffff, 0), 738 .yrgb_vir = VOP_REG(RV1126_WIN2_VIR0_1, 0x1fff, 0), 739 }; 740 741 static const struct vop_ctrl rv1126_ctrl_data = { 742 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 743 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 744 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 745 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 746 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 747 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 748 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 749 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 750 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 751 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 752 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 753 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 754 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22), 755 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 756 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 757 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 758 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 759 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 760 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 761 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 762 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 763 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 764 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 765 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 766 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 767 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 768 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 769 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 770 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8), 771 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 772 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 773 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9), 774 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11), 775 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12), 776 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 777 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 778 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 779 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 780 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 781 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 782 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 783 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 784 785 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 786 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 787 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 788 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 789 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 790 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 791 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 792 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 793 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 794 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 795 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 796 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 797 798 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 799 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 800 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 801 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 802 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 803 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 804 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 805 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 806 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 807 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 808 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 809 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 810 0xffffffff, 0), 811 }; 812 813 static const struct vop_grf_ctrl rv1126_grf_ctrl = { 814 .grf_dclk_inv = VOP_REG(0x1026c, 0x1, 2), 815 }; 816 817 const struct vop_data rv1126_vop = { 818 .version = VOP_VERSION(2, 7), 819 .max_output = {1920, 1080}, 820 .ctrl = &rv1126_ctrl_data, 821 .grf_ctrl = &rv1126_grf_ctrl, 822 .win = &rv1126_win2_data, 823 .line_flag = &rk3366_vop_lite_line_flag, 824 .reg_len = RK3366_LIT_FLAG_REG * 4, 825 }; 826 827 static const struct vop_ctrl rv1106_ctrl_data = { 828 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 829 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 830 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 831 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 832 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 833 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 834 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 835 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 836 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 837 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 838 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 839 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 840 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 841 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 842 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 843 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 844 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 845 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8), 846 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 847 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 848 .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9), 849 .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11), 850 .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12), 851 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 852 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 853 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 854 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 855 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 856 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 857 858 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 859 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 860 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 861 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 862 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 863 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 864 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 865 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 866 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 867 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 868 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 869 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 870 871 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 872 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 873 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 874 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 875 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 876 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 877 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 878 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 879 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 880 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 881 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 882 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 883 0xffffffff, 0), 884 .bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30), 885 .bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31), 886 .bt656_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 6), 887 }; 888 889 static const struct vop_grf_ctrl rv1106_grf_ctrl = { 890 .grf_dclk_inv = VOP_REG(0x1000c, 0x1, 2), 891 }; 892 893 static const struct vop_win rv1106_win1_data = { 894 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 895 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 896 .interlace_read = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 8), 897 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 898 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0x0fff0fff, 0), 899 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 900 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 901 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 902 903 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 904 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 905 }; 906 907 static const struct vop_line_flag rv1106_vop_lite_line_flag = { 908 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 909 .line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16), 910 }; 911 912 const struct vop_data rv1106_vop = { 913 .version = VOP_VERSION(2, 12), 914 .max_output = {1280, 1280}, 915 .ctrl = &rv1106_ctrl_data, 916 .grf_ctrl = &rv1106_grf_ctrl, 917 .win = &rv1106_win1_data, 918 .line_flag = &rv1106_vop_lite_line_flag, 919 .reg_len = RK3366_LIT_FLAG_REG * 4, 920 }; 921