1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _ROCKCHIP_CRTC_H_ 8*4882a593Smuzhiyun #define _ROCKCHIP_CRTC_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define VOP2_MAX_VP 4 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct rockchip_vp { 13*4882a593Smuzhiyun bool enable; 14*4882a593Smuzhiyun bool xmirror_en; 15*4882a593Smuzhiyun u8 bg_ovl_dly; 16*4882a593Smuzhiyun u8 primary_plane_id; 17*4882a593Smuzhiyun int output_type; 18*4882a593Smuzhiyun u32 plane_mask; 19*4882a593Smuzhiyun int cursor_plane; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct rockchip_crtc { 23*4882a593Smuzhiyun const struct rockchip_crtc_funcs *funcs; 24*4882a593Smuzhiyun const void *data; 25*4882a593Smuzhiyun struct drm_display_mode active_mode; 26*4882a593Smuzhiyun struct rockchip_vp vps[4]; 27*4882a593Smuzhiyun bool hdmi_hpd : 1; 28*4882a593Smuzhiyun bool active : 1; 29*4882a593Smuzhiyun bool assign_plane : 1; 30*4882a593Smuzhiyun bool splice_mode : 1; 31*4882a593Smuzhiyun u8 splice_crtc_id; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct rockchip_crtc_funcs { 35*4882a593Smuzhiyun int (*preinit)(struct display_state *state); 36*4882a593Smuzhiyun int (*init)(struct display_state *state); 37*4882a593Smuzhiyun void (*deinit)(struct display_state *state); 38*4882a593Smuzhiyun int (*set_plane)(struct display_state *state); 39*4882a593Smuzhiyun int (*prepare)(struct display_state *state); 40*4882a593Smuzhiyun int (*enable)(struct display_state *state); 41*4882a593Smuzhiyun int (*disable)(struct display_state *state); 42*4882a593Smuzhiyun void (*unprepare)(struct display_state *state); 43*4882a593Smuzhiyun int (*fixup_dts)(struct display_state *state, void *blob); 44*4882a593Smuzhiyun int (*send_mcu_cmd)(struct display_state *state, u32 type, u32 value); 45*4882a593Smuzhiyun int (*check)(struct display_state *state); 46*4882a593Smuzhiyun int (*mode_valid)(struct display_state *state); 47*4882a593Smuzhiyun int (*mode_fixup)(struct display_state *state); 48*4882a593Smuzhiyun int (*plane_check)(struct display_state *state); 49*4882a593Smuzhiyun int (*regs_dump)(struct display_state *state); 50*4882a593Smuzhiyun int (*active_regs_dump)(struct display_state *state); 51*4882a593Smuzhiyun int (*apply_soft_te)(struct display_state *state); 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct vop_data; 55*4882a593Smuzhiyun struct vop2_data; 56*4882a593Smuzhiyun extern const struct rockchip_crtc_funcs rockchip_vop_funcs; 57*4882a593Smuzhiyun extern const struct rockchip_crtc_funcs rockchip_vop2_funcs; 58*4882a593Smuzhiyun extern const struct vop_data rk3036_vop; 59*4882a593Smuzhiyun extern const struct vop_data px30_vop_lit; 60*4882a593Smuzhiyun extern const struct vop_data px30_vop_big; 61*4882a593Smuzhiyun extern const struct vop_data rk3308_vop; 62*4882a593Smuzhiyun extern const struct vop_data rk1808_vop; 63*4882a593Smuzhiyun extern const struct vop_data rk3288_vop_big; 64*4882a593Smuzhiyun extern const struct vop_data rk3288_vop_lit; 65*4882a593Smuzhiyun extern const struct vop_data rk3368_vop; 66*4882a593Smuzhiyun extern const struct vop_data rk3366_vop; 67*4882a593Smuzhiyun extern const struct vop_data rk3399_vop_big; 68*4882a593Smuzhiyun extern const struct vop_data rk3399_vop_lit; 69*4882a593Smuzhiyun extern const struct vop_data rk322x_vop; 70*4882a593Smuzhiyun extern const struct vop_data rk3328_vop; 71*4882a593Smuzhiyun extern const struct vop_data rv1106_vop; 72*4882a593Smuzhiyun extern const struct vop_data rv1108_vop; 73*4882a593Smuzhiyun extern const struct vop_data rv1126_vop; 74*4882a593Smuzhiyun extern const struct vop2_data rk3528_vop; 75*4882a593Smuzhiyun extern const struct vop2_data rk3562_vop; 76*4882a593Smuzhiyun extern const struct vop2_data rk3568_vop; 77*4882a593Smuzhiyun extern const struct vop2_data rk3588_vop; 78*4882a593Smuzhiyun #endif 79