1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <dm/device-internal.h>
11 #include <drm/drm_mipi_dsi.h>
12 #include <video_bridge.h>
13 #include <asm/unaligned.h>
14 #include <linux/math64.h>
15
16 #include "rockchip_display.h"
17 #include "rockchip_bridge.h"
18 #include "rk618.h"
19
20 /* host registers */
21 #define HOSTREG(x) ((x) + 0x1000)
22 #define DSI_VERSION HOSTREG(0x0000)
23 #define DSI_PWR_UP HOSTREG(0x0004)
24 #define SHUTDOWNZ BIT(0)
25 #define POWER_UP BIT(0)
26 #define RESET 0
27 #define DSI_CLKMGR_CFG HOSTREG(0x0008)
28 #define TO_CLK_DIVIDSION(x) UPDATE(x, 15, 8)
29 #define TX_ESC_CLK_DIVIDSION(x) UPDATE(x, 7, 0)
30 #define DSI_DPI_CFG HOSTREG(0x000c)
31 #define EN18_LOOSELY BIT(10)
32 #define COLORM_ACTIVE_LOW BIT(9)
33 #define SHUTD_ACTIVE_LOW BIT(8)
34 #define HSYNC_ACTIVE_LOW BIT(7)
35 #define VSYNC_ACTIVE_LOW BIT(6)
36 #define DATAEN_ACTIVE_LOW BIT(5)
37 #define DPI_COLOR_CODING(x) UPDATE(x, 4, 2)
38 #define DPI_VID(x) UPDATE(x, 1, 0)
39 #define DSI_PCKHDL_CFG HOSTREG(0x0018)
40 #define GEN_VID_RX(x) UPDATE(x, 6, 5)
41 #define EN_CRC_RX BIT(4)
42 #define EN_ECC_RX BIT(3)
43 #define EN_BTA BIT(2)
44 #define EN_EOTP_RX BIT(1)
45 #define EN_EOTP_TX BIT(0)
46 #define DSI_VID_MODE_CFG HOSTREG(0x001c)
47 #define LPCMDEN BIT(12)
48 #define FRAME_BTA_ACK BIT(11)
49 #define EN_NULL_PKT BIT(10)
50 #define EN_MULTI_PKT BIT(9)
51 #define EN_LP_HFP BIT(8)
52 #define EN_LP_HBP BIT(7)
53 #define EN_LP_VACT BIT(6)
54 #define EN_LP_VFP BIT(5)
55 #define EN_LP_VBP BIT(4)
56 #define EN_LP_VSA BIT(3)
57 #define VID_MODE_TYPE(x) UPDATE(x, 2, 1)
58 #define EN_VIDEO_MODE BIT(0)
59 #define DSI_VID_PKT_CFG HOSTREG(0x0020)
60 #define NULL_PKT_SIZE(x) UPDATE(x, 30, 21)
61 #define NUM_CHUNKS(x) UPDATE(x, 20, 11)
62 #define VID_PKT_SIZE(x) UPDATE(x, 10, 0)
63 #define DSI_CMD_MODE_CFG HOSTREG(0x0024)
64 #define TEAR_FX_EN BIT(14)
65 #define ACK_RQST_EN BIT(13)
66 #define DCS_LW_TX BIT(12)
67 #define GEN_LW_TX BIT(11)
68 #define MAX_RD_PKT_SIZE BIT(10)
69 #define DCS_SR_0P_TX BIT(9)
70 #define DCS_SW_1P_TX BIT(8)
71 #define DCS_SW_0P_TX BIT(7)
72 #define GEN_SR_2P_TX BIT(6)
73 #define GEN_SR_1P_TX BIT(5)
74 #define GEN_SR_0P_TX BIT(4)
75 #define GEN_SW_2P_TX BIT(3)
76 #define GEN_SW_1P_TX BIT(2)
77 #define GEN_SW_0P_TX BIT(1)
78 #define EN_CMD_MODE BIT(0)
79 #define DSI_TMR_LINE_CFG HOSTREG(0x0028)
80 #define HLINE_TIME(x) UPDATE(x, 31, 18)
81 #define HBP_TIME(x) UPDATE(x, 17, 9)
82 #define HSA_TIME(x) UPDATE(x, 8, 0)
83 #define DSI_VTIMING_CFG HOSTREG(0x002c)
84 #define V_ACTIVE_LINES(x) UPDATE(x, 26, 16)
85 #define VFP_LINES(x) UPDATE(x, 15, 10)
86 #define VBP_LINES(x) UPDATE(x, 9, 4)
87 #define VSA_LINES(x) UPDATE(x, 3, 0)
88 #define DSI_PHY_TMR_CFG HOSTREG(0x0030)
89 #define PHY_HS2LP_TIME(x) UPDATE(x, 31, 24)
90 #define PHY_LP2HS_TIME(x) UPDATE(x, 23, 16)
91 #define MAX_RD_TIME(x) UPDATE(x, 14, 0)
92 #define DSI_GEN_HDR HOSTREG(0x0034)
93 #define DSI_GEN_PLD_DATA HOSTREG(0x0038)
94 #define DSI_GEN_PKT_STATUS HOSTREG(0x003c)
95 #define GEN_RD_CMD_BUSY BIT(6)
96 #define GEN_PLD_R_FULL BIT(5)
97 #define GEN_PLD_R_EMPTY BIT(4)
98 #define GEN_PLD_W_FULL BIT(3)
99 #define GEN_PLD_W_EMPTY BIT(2)
100 #define GEN_CMD_FULL BIT(1)
101 #define GEN_CMD_EMPTY BIT(0)
102 #define DSI_TO_CNT_CFG HOSTREG(0x0040)
103 #define LPRX_TO_CNT(x) UPDATE(x, 31, 16)
104 #define HSTX_TO_CNT(x) UPDATE(x, 15, 0)
105 #define DSI_INT_ST0 HOSTREG(0x0044)
106 #define DSI_INT_ST1 HOSTREG(0x0048)
107 #define DSI_INT_MSK0 HOSTREG(0x004c)
108 #define DSI_INT_MSK1 HOSTREG(0x0050)
109 #define DSI_PHY_RSTZ HOSTREG(0x0054)
110 #define PHY_ENABLECLK BIT(2)
111 #define DSI_PHY_IF_CFG HOSTREG(0x0058)
112 #define PHY_STOP_WAIT_TIME(x) UPDATE(x, 9, 2)
113 #define N_LANES(x) UPDATE(x, 1, 0)
114 #define DSI_PHY_IF_CTRL HOSTREG(0x005c)
115 #define PHY_TX_TRIGGERS(x) UPDATE(x, 8, 5)
116 #define PHY_TXEXITULPSLAN BIT(4)
117 #define PHY_TXREQULPSLAN BIT(3)
118 #define PHY_TXEXITULPSCLK BIT(2)
119 #define PHY_RXREQULPSCLK BIT(1)
120 #define PHY_TXREQUESCLKHS BIT(0)
121 #define DSI_PHY_STATUS HOSTREG(0x0060)
122 #define ULPSACTIVENOT3LANE BIT(12)
123 #define PHYSTOPSTATE3LANE BIT(11)
124 #define ULPSACTIVENOT2LANE BIT(10)
125 #define PHYSTOPSTATE2LANE BIT(9)
126 #define ULPSACTIVENOT1LANE BIT(8)
127 #define PHYSTOPSTATE1LANE BIT(7)
128 #define RXULPSESC0LANE BIT(6)
129 #define ULPSACTIVENOT0LANE BIT(5)
130 #define PHYSTOPSTATE0LANE BIT(4)
131 #define PHYULPSACTIVENOTCLK BIT(3)
132 #define PHYSTOPSTATECLKLANE BIT(2)
133 #define PHYSTOPSTATELANE (PHYSTOPSTATE0LANE | PHYSTOPSTATECLKLANE)
134 #define PHYDIRECTION BIT(1)
135 #define PHYLOCK BIT(0)
136 #define DSI_LP_CMD_TIM HOSTREG(0x0070)
137 #define OUTVACT_LPCMD_TIME(x) UPDATE(x, 15, 8)
138 #define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0)
139 #define DSI_MAX_REGISTER DSI_LP_CMD_TIM
140
141 /* phy registers */
142 #define PHYREG(x) ((x) + 0x0c00)
143 #define MIPI_PHY_REG0 PHYREG(0x0000)
144 #define LANE_EN_MASK GENMASK(6, 2)
145 #define LANE_EN_CK BIT(6)
146 #define MIPI_PHY_REG1 PHYREG(0x0004)
147 #define REG_DA_PPFC BIT(4)
148 #define REG_DA_SYNCRST BIT(2)
149 #define REG_DA_LDOPD BIT(1)
150 #define REG_DA_PLLPD BIT(0)
151 #define MIPI_PHY_REG3 PHYREG(0x000c)
152 #define REG_FBDIV_HI_MASK GENMASK(5, 5)
153 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
154 #define REG_PREDIV_MASK GENMASK(4, 0)
155 #define REG_PREDIV(x) UPDATE(x, 4, 0)
156 #define MIPI_PHY_REG4 PHYREG(0x0010)
157 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
158 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
159 #define MIPI_PHY_REG5 PHYREG(0x0014)
160 #define MIPI_PHY_REG6 PHYREG(0x0018)
161 #define MIPI_PHY_REG7 PHYREG(0x001c)
162 #define MIPI_PHY_REG9 PHYREG(0x0024)
163 #define MIPI_PHY_REG20 PHYREG(0x0080)
164 #define REG_DIG_RSTN BIT(0)
165 #define MIPI_PHY_MAX_REGISTER PHYREG(0x0348)
166
167 #define THS_SETTLE_OFFSET 0x00
168 #define THS_SETTLE_MASK GENMASK(3, 0)
169 #define THS_SETTLE(x) UPDATE(x, 3, 0)
170 #define TLPX_OFFSET 0x14
171 #define TLPX_MASK GENMASK(5, 0)
172 #define TLPX(x) UPDATE(x, 5, 0)
173 #define THS_PREPARE_OFFSET 0x18
174 #define THS_PREPARE_MASK GENMASK(6, 0)
175 #define THS_PREPARE(x) UPDATE(x, 6, 0)
176 #define THS_ZERO_OFFSET 0x1c
177 #define THS_ZERO_MASK GENMASK(5, 0)
178 #define THS_ZERO(x) UPDATE(x, 5, 0)
179 #define THS_TRAIL_OFFSET 0x20
180 #define THS_TRAIL_MASK GENMASK(6, 0)
181 #define THS_TRAIL(x) UPDATE(x, 6, 0)
182 #define THS_EXIT_OFFSET 0x24
183 #define THS_EXIT_MASK GENMASK(4, 0)
184 #define THS_EXIT(x) UPDATE(x, 4, 0)
185 #define TCLK_POST_OFFSET 0x28
186 #define TCLK_POST_MASK GENMASK(3, 0)
187 #define TCLK_POST(x) UPDATE(x, 3, 0)
188 #define TWAKUP_HI_OFFSET 0x30
189 #define TWAKUP_HI_MASK GENMASK(1, 0)
190 #define TWAKUP_HI(x) UPDATE(x, 1, 0)
191 #define TWAKUP_LO_OFFSET 0x34
192 #define TWAKUP_LO_MASK GENMASK(7, 0)
193 #define TWAKUP_LO(x) UPDATE(x, 7, 0)
194 #define TCLK_PRE_OFFSET 0x38
195 #define TCLK_PRE_MASK GENMASK(3, 0)
196 #define TCLK_PRE(x) UPDATE(x, 3, 0)
197 #define TTA_GO_OFFSET 0x40
198 #define TTA_GO_MASK GENMASK(5, 0)
199 #define TTA_GO(x) UPDATE(x, 5, 0)
200 #define TTA_SURE_OFFSET 0x44
201 #define TTA_SURE_MASK GENMASK(5, 0)
202 #define TTA_SURE(x) UPDATE(x, 5, 0)
203 #define TTA_WAIT_OFFSET 0x48
204 #define TTA_WAIT_MASK GENMASK(5, 0)
205 #define TTA_WAIT(x) UPDATE(x, 5, 0)
206
207 #define USEC_PER_SEC 1000000L
208 #define USEC_PER_MSEC 1000L
209 #define PSEC_PER_NSEC 1000L
210 #define PSEC_PER_SEC 1000000000000LL
211
212 struct mipi_dphy {
213 u8 prediv;
214 u16 fbdiv;
215 unsigned int rate;
216 };
217
218 struct rk618_dsi {
219 struct udevice *dev;
220 struct rk618 *parent;
221 struct mipi_dphy phy;
222 unsigned int channel;
223 unsigned int lanes;
224 enum mipi_dsi_pixel_format format;
225 unsigned long mode_flags;
226 struct drm_display_mode mode;
227 };
228
229 enum {
230 NON_BURST_MODE_SYNC_PULSE,
231 NON_BURST_MODE_SYNC_EVENT,
232 BURST_MODE,
233 };
234
235 enum {
236 PIXEL_COLOR_CODING_16BIT_1,
237 PIXEL_COLOR_CODING_16BIT_2,
238 PIXEL_COLOR_CODING_16BIT_3,
239 PIXEL_COLOR_CODING_18BIT_1,
240 PIXEL_COLOR_CODING_18BIT_2,
241 PIXEL_COLOR_CODING_24BIT,
242 };
243
244 #define dsi_read_poll_timeout(dsi, addr, val, cond, sleep_us, timeout_us) \
245 ({ \
246 unsigned long timeout = timer_get_us() + (timeout_us); \
247 for (;;) { \
248 (val) = dsi_read(dsi, addr); \
249 if (cond) \
250 break; \
251 if ((timeout_us) && time_after(timer_get_us(), timeout)) { \
252 (val) = dsi_read(dsi, addr); \
253 break; \
254 } \
255 if (sleep_us) \
256 udelay(sleep_us); \
257 } \
258 (cond) ? 0 : -ETIMEDOUT; \
259 })
260
dsi_write(struct rk618_dsi * dsi,u32 reg,u32 val)261 static inline int dsi_write(struct rk618_dsi *dsi, u32 reg, u32 val)
262 {
263 return rk618_i2c_write(dsi->parent, reg, val);
264 }
265
dsi_read(struct rk618_dsi * dsi,u32 reg)266 static inline u32 dsi_read(struct rk618_dsi *dsi, u32 reg)
267 {
268 u32 val;
269
270 rk618_i2c_read(dsi->parent, reg, &val);
271
272 return val;
273 }
274
dsi_update_bits(struct rk618_dsi * dsi,u32 reg,u32 mask,u32 val)275 static inline void dsi_update_bits(struct rk618_dsi *dsi,
276 u32 reg, u32 mask, u32 val)
277 {
278 u32 orig, tmp;
279
280 orig = dsi_read(dsi, reg);
281 tmp = orig & ~mask;
282 tmp |= val & mask;
283 dsi_write(dsi, reg, tmp);
284 }
285
is_clk_lane(u32 offset)286 static inline bool is_clk_lane(u32 offset)
287 {
288 if (offset == 0x100)
289 return true;
290
291 return false;
292 }
293
rk618_dsi_set_hs_clk(struct rk618_dsi * dsi)294 static void rk618_dsi_set_hs_clk(struct rk618_dsi *dsi)
295 {
296 const struct drm_display_mode *mode = &dsi->mode;
297 struct mipi_dphy *phy = &dsi->phy;
298 u32 fout, fref, prediv, fbdiv;
299 u32 min_delta = UINT_MAX;
300 unsigned int value;
301
302 value = dev_read_u32_default(dsi->dev, "rockchip,lane-rate", 0);
303 if (value > 0) {
304 fout = value * USEC_PER_SEC;
305 } else {
306 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
307 unsigned int lanes = dsi->lanes;
308 u64 bandwidth;
309
310 bandwidth = (u64)mode->clock * 1000 * bpp;
311 do_div(bandwidth, lanes);
312
313 /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
314 bandwidth *= 10;
315 do_div(bandwidth, 9);
316
317 do_div(bandwidth, USEC_PER_SEC);
318 bandwidth *= USEC_PER_SEC;
319 fout = bandwidth;
320 }
321
322 if (fout > 1000000000UL)
323 fout = 1000000000UL;
324
325 fref = clk_get_rate(&dsi->parent->clkin);
326
327 for (prediv = 1; prediv <= 12; prediv++) {
328 u64 tmp;
329 u32 delta;
330
331 if (fref % prediv)
332 continue;
333
334 tmp = (u64)fout * prediv;
335 do_div(tmp, fref);
336 fbdiv = tmp;
337
338 if (fbdiv < 12 || fbdiv > 511)
339 continue;
340
341 if (fbdiv == 15)
342 continue;
343
344 tmp = (u64)fbdiv * fref;
345 do_div(tmp, prediv);
346
347 delta = abs(fout - tmp);
348 if (!delta) {
349 phy->rate = tmp;
350 phy->prediv = prediv;
351 phy->fbdiv = fbdiv;
352 break;
353 } else if (delta < min_delta) {
354 phy->rate = tmp;
355 phy->prediv = prediv;
356 phy->fbdiv = fbdiv;
357 min_delta = delta;
358 }
359 }
360 }
361
rk618_dsi_phy_power_off(struct rk618_dsi * dsi)362 static void rk618_dsi_phy_power_off(struct rk618_dsi *dsi)
363 {
364 dsi_update_bits(dsi, MIPI_PHY_REG0, LANE_EN_MASK, 0);
365 dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_LDOPD | REG_DA_PLLPD,
366 REG_DA_LDOPD | REG_DA_PLLPD);
367 }
368
rk618_dsi_phy_power_on(struct rk618_dsi * dsi,u32 txclkesc)369 static void rk618_dsi_phy_power_on(struct rk618_dsi *dsi, u32 txclkesc)
370 {
371 struct mipi_dphy *phy = &dsi->phy;
372 u32 offset, value, index;
373 const struct {
374 unsigned int rate;
375 u8 ths_settle;
376 u8 ths_zero;
377 u8 ths_trail;
378 } timing_table[] = {
379 { 110000000, 0x00, 0x03, 0x0c},
380 { 150000000, 0x01, 0x04, 0x0d},
381 { 200000000, 0x02, 0x04, 0x11},
382 { 250000000, 0x03, 0x05, 0x14},
383 { 300000000, 0x04, 0x06, 0x18},
384 { 400000000, 0x05, 0x07, 0x1d},
385 { 500000000, 0x06, 0x08, 0x23},
386 { 600000000, 0x07, 0x0a, 0x29},
387 { 700000000, 0x08, 0x0b, 0x31},
388 { 800000000, 0x09, 0x0c, 0x34},
389 {1000000000, 0x0a, 0x0f, 0x40},
390 };
391 u32 Ttxbyteclkhs, UI, Ttxddrclkhs, Ttxclkesc;
392 u32 Tlpx, Ths_exit, Tclk_post, Tclk_pre, Ths_prepare;
393 u32 Tta_go, Tta_sure, Tta_wait;
394
395 Ttxbyteclkhs = div_u64(PSEC_PER_SEC, phy->rate / 8);
396 UI = Ttxddrclkhs = div_u64(PSEC_PER_SEC, phy->rate);
397 Ttxclkesc = div_u64(PSEC_PER_SEC, txclkesc);
398
399 dsi_update_bits(dsi, MIPI_PHY_REG3, REG_FBDIV_HI_MASK |
400 REG_PREDIV_MASK, REG_FBDIV_HI(phy->fbdiv >> 8) |
401 REG_PREDIV(phy->prediv));
402 dsi_update_bits(dsi, MIPI_PHY_REG4,
403 REG_FBDIV_LO_MASK, REG_FBDIV_LO(phy->fbdiv));
404 dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_LDOPD | REG_DA_PLLPD, 0);
405
406 dsi_update_bits(dsi, MIPI_PHY_REG0, LANE_EN_MASK,
407 LANE_EN_CK | GENMASK(dsi->lanes - 1 + 2, 2));
408
409 dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_SYNCRST, REG_DA_SYNCRST);
410 udelay(1);
411 dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_SYNCRST, 0);
412
413 dsi_update_bits(dsi, MIPI_PHY_REG20, REG_DIG_RSTN, 0);
414 udelay(1);
415 dsi_update_bits(dsi, MIPI_PHY_REG20, REG_DIG_RSTN, REG_DIG_RSTN);
416
417 /* XXX */
418 dsi_write(dsi, MIPI_PHY_REG6, 0x11);
419 dsi_write(dsi, MIPI_PHY_REG7, 0x11);
420 dsi_write(dsi, MIPI_PHY_REG9, 0xcc);
421
422 if (phy->rate < 800000000)
423 dsi_update_bits(dsi, MIPI_PHY_REG1, REG_DA_PPFC, REG_DA_PPFC);
424 else
425 dsi_write(dsi, MIPI_PHY_REG5, 0x30);
426
427 for (index = 0; index < ARRAY_SIZE(timing_table); index++)
428 if (phy->rate <= timing_table[index].rate)
429 break;
430
431 if (index == ARRAY_SIZE(timing_table))
432 --index;
433
434 for (offset = 0x100; offset <= 0x300; offset += 0x80) {
435 dsi_update_bits(dsi, PHYREG(offset + THS_SETTLE_OFFSET),
436 THS_SETTLE_MASK,
437 THS_SETTLE(timing_table[index].ths_settle));
438
439 /*
440 * The value of counter for HS Tlpx Time
441 * Tlpx = Tpin_txbyteclkhs * value
442 */
443 Tlpx = 60 * PSEC_PER_NSEC;
444 value = DIV_ROUND_UP(Tlpx, Ttxbyteclkhs);
445 Tlpx = Ttxbyteclkhs * value;
446 dsi_update_bits(dsi, PHYREG(offset + TLPX_OFFSET),
447 TLPX_MASK, TLPX(value));
448
449 /*
450 * The value of counter for HS Ths-prepare
451 * For clock lane, Ths-prepare(38ns~95ns)
452 * For data lane, Ths-prepare(40ns+4UI~85ns+6UI)
453 * Ths-prepare = Ttxddrclkhs * value
454 */
455 if (is_clk_lane(offset))
456 Ths_prepare = 65 * PSEC_PER_NSEC;
457 else
458 Ths_prepare = 65 * PSEC_PER_NSEC + 4 * UI;
459
460 value = DIV_ROUND_UP(Ths_prepare, Ttxddrclkhs);
461 dsi_update_bits(dsi, PHYREG(offset + THS_PREPARE_OFFSET),
462 THS_PREPARE_MASK, THS_PREPARE(value));
463
464 dsi_update_bits(dsi, PHYREG(offset + THS_ZERO_OFFSET),
465 THS_ZERO_MASK,
466 THS_ZERO(timing_table[index].ths_zero));
467
468 dsi_update_bits(dsi, PHYREG(offset + THS_TRAIL_OFFSET),
469 THS_TRAIL_MASK,
470 THS_TRAIL(timing_table[index].ths_trail));
471
472 /*
473 * The value of counter for HS Ths-exit
474 * Ths-exit = Tpin_txbyteclkhs * value
475 */
476 Ths_exit = 120 * PSEC_PER_NSEC;
477 value = DIV_ROUND_UP(Ths_exit, Ttxbyteclkhs);
478 dsi_update_bits(dsi, PHYREG(offset + THS_EXIT_OFFSET),
479 THS_EXIT_MASK, THS_EXIT(value));
480
481 /*
482 * The value of counter for HS Tclk-post
483 * Tclk-post = Ttxbyteclkhs * value
484 */
485 Tclk_post = 70 * PSEC_PER_NSEC + 52 * UI;
486 value = DIV_ROUND_UP(Tclk_post, Ttxbyteclkhs);
487 dsi_update_bits(dsi, PHYREG(offset + TCLK_POST_OFFSET),
488 TCLK_POST_MASK, TCLK_POST(value));
489
490 /*
491 * The value of counter for HS Twakup
492 * Twakup for ulpm,
493 * Twakup = Tpin_sys_clk * value
494 */
495 dsi_update_bits(dsi, PHYREG(offset + TWAKUP_HI_OFFSET),
496 TWAKUP_HI_MASK, TWAKUP_HI(0x3));
497 dsi_update_bits(dsi, PHYREG(offset + TWAKUP_LO_OFFSET),
498 TWAKUP_LO_MASK, TWAKUP_LO(0xff));
499
500 /*
501 * The value of counter for HS Tclk-pre
502 * Tclk-pre for clock lane
503 * Tclk-pre = Tpin_txbyteclkhs * value
504 */
505 Tclk_pre = 8 * UI;
506 value = DIV_ROUND_UP(Tclk_pre, Ttxbyteclkhs);
507 dsi_update_bits(dsi, PHYREG(offset + TCLK_PRE_OFFSET),
508 TCLK_PRE_MASK, TCLK_PRE(value));
509
510 /*
511 * The value of counter for HS Tta-go
512 * Tta-go for turnaround
513 * Tta-go = Ttxclkesc * value
514 */
515 Tta_go = 4 * Tlpx;
516 value = DIV_ROUND_UP(Tta_go, Ttxclkesc);
517 dsi_update_bits(dsi, PHYREG(offset + TTA_GO_OFFSET),
518 TTA_GO_MASK, TTA_GO(value));
519
520 /*
521 * The value of counter for HS Tta-sure
522 * Tta-sure for turnaround
523 * Tta-sure = Ttxclkesc * value
524 */
525 Tta_sure = 2 * Tlpx;
526 value = DIV_ROUND_UP(Tta_sure, Ttxclkesc);
527 dsi_update_bits(dsi, PHYREG(offset + TTA_SURE_OFFSET),
528 TTA_SURE_MASK, TTA_SURE(value));
529
530 /*
531 * The value of counter for HS Tta-wait
532 * Tta-wait for turnaround
533 * Interval from receiving ppi turnaround request to
534 * sending esc request.
535 * Tta-wait = Ttxclkesc * value
536 */
537 Tta_wait = 5 * Tlpx;
538 value = DIV_ROUND_UP(Tta_wait, Ttxclkesc);
539 dsi_update_bits(dsi, PHYREG(offset + TTA_WAIT_OFFSET),
540 TTA_WAIT_MASK, TTA_WAIT(value));
541 }
542 }
543
rk618_dsi_pre_enable(struct rk618_dsi * dsi)544 static int rk618_dsi_pre_enable(struct rk618_dsi *dsi)
545 {
546 struct drm_display_mode *mode = &dsi->mode;
547 u32 esc_clk_div, txclkesc;
548 u32 lanebyteclk, dpipclk;
549 u32 hsw, hbp, vsw, vfp, vbp;
550 u32 hsa_time, hbp_time, hline_time;
551 u32 value;
552 int ret;
553
554 rk618_dsi_set_hs_clk(dsi);
555
556 dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
557
558 /* Configuration of the internal clock dividers */
559 esc_clk_div = DIV_ROUND_UP(dsi->phy.rate >> 3, 20000000);
560 txclkesc = dsi->phy.rate >> 3 / esc_clk_div;
561 value = TO_CLK_DIVIDSION(10) | TX_ESC_CLK_DIVIDSION(esc_clk_div);
562 dsi_write(dsi, DSI_CLKMGR_CFG, value);
563
564 /* The DPI interface configuration */
565 value = DPI_VID(dsi->channel);
566
567 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
568 value |= VSYNC_ACTIVE_LOW;
569 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
570 value |= HSYNC_ACTIVE_LOW;
571
572 switch (dsi->format) {
573 case MIPI_DSI_FMT_RGB666:
574 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_18BIT_2);
575 break;
576 case MIPI_DSI_FMT_RGB666_PACKED:
577 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_18BIT_1);
578 value |= EN18_LOOSELY;
579 break;
580 case MIPI_DSI_FMT_RGB565:
581 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_16BIT_1);
582 break;
583 case MIPI_DSI_FMT_RGB888:
584 default:
585 value |= DPI_COLOR_CODING(PIXEL_COLOR_CODING_24BIT);
586 break;
587 }
588
589 dsi_write(dsi, DSI_DPI_CFG, value);
590
591 /* Packet handler configuration */
592 value = GEN_VID_RX(dsi->channel) | EN_CRC_RX | EN_ECC_RX | EN_BTA;
593
594 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
595 value |= EN_EOTP_TX;
596
597 dsi_write(dsi, DSI_PCKHDL_CFG, value);
598
599 /* Video mode configuration */
600 value = EN_LP_VACT | EN_LP_VBP | EN_LP_VFP | EN_LP_VSA;
601
602 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
603 value |= EN_LP_HFP;
604
605 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
606 value |= EN_LP_HBP;
607
608 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
609 value |= VID_MODE_TYPE(BURST_MODE);
610 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
611 value |= VID_MODE_TYPE(NON_BURST_MODE_SYNC_PULSE);
612 else
613 value |= VID_MODE_TYPE(NON_BURST_MODE_SYNC_EVENT);
614
615 dsi_write(dsi, DSI_VID_MODE_CFG, value);
616
617 /* Video packet configuration */
618 dsi_write(dsi, DSI_VID_PKT_CFG, VID_PKT_SIZE(mode->hdisplay));
619
620 /* Timeout timers configuration */
621 dsi_write(dsi, DSI_TO_CNT_CFG, LPRX_TO_CNT(1000) | HSTX_TO_CNT(1000));
622
623 hsw = mode->hsync_end - mode->hsync_start;
624 hbp = mode->htotal - mode->hsync_end;
625 vsw = mode->vsync_end - mode->vsync_start;
626 vfp = mode->vsync_start - mode->vdisplay;
627 vbp = mode->vtotal - mode->vsync_end;
628
629 /* Line timing configuration */
630 lanebyteclk = (dsi->phy.rate >> 3) / USEC_PER_SEC;
631 dpipclk = mode->clock / USEC_PER_MSEC;
632 hline_time = DIV_ROUND_UP(mode->htotal * lanebyteclk, dpipclk);
633 hbp_time = DIV_ROUND_UP(hbp * lanebyteclk, dpipclk);
634 hsa_time = DIV_ROUND_UP(hsw * lanebyteclk, dpipclk);
635 dsi_write(dsi, DSI_TMR_LINE_CFG, HLINE_TIME(hline_time) |
636 HBP_TIME(hbp_time) | HSA_TIME(hsa_time));
637
638 /* Vertical timing configuration */
639 dsi_write(dsi, DSI_VTIMING_CFG,
640 V_ACTIVE_LINES(mode->vdisplay) | VFP_LINES(vfp) |
641 VBP_LINES(vbp) | VSA_LINES(vsw));
642
643 /* D-PHY interface configuration */
644 value = N_LANES(dsi->lanes - 1) | PHY_STOP_WAIT_TIME(0x20);
645 dsi_write(dsi, DSI_PHY_IF_CFG, value);
646
647 /* D-PHY timing configuration */
648 value = PHY_HS2LP_TIME(20) | PHY_LP2HS_TIME(16) | MAX_RD_TIME(10000);
649 dsi_write(dsi, DSI_PHY_TMR_CFG, value);
650
651 /* enables the D-PHY Clock Lane Module */
652 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
653
654 dsi_update_bits(dsi, DSI_VID_MODE_CFG, EN_VIDEO_MODE, 0);
655 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, EN_CMD_MODE, EN_CMD_MODE);
656
657 rk618_dsi_phy_power_on(dsi, txclkesc);
658
659 /* wait for the PHY to acquire lock */
660 ret = dsi_read_poll_timeout(dsi, DSI_PHY_STATUS,
661 value, value & PHYLOCK, 50, 1000);
662 if (ret) {
663 dev_err(dsi->dev, "PHY is not locked\n");
664 return ret;
665 }
666
667 /* wait for the lane go to the stop state */
668 ret = dsi_read_poll_timeout(dsi, DSI_PHY_STATUS,
669 value, value & PHYSTOPSTATELANE, 50, 1000);
670 if (ret) {
671 dev_err(dsi->dev, "lane module is not in stop state\n");
672 return ret;
673 }
674
675 dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
676
677 return 0;
678 }
679
rk618_dsi_enable(struct rk618_dsi * dsi)680 static void rk618_dsi_enable(struct rk618_dsi *dsi)
681 {
682 /* controls the D-PHY PPI txrequestclkhs signal */
683 dsi_update_bits(dsi, DSI_PHY_IF_CTRL,
684 PHY_TXREQUESCLKHS, PHY_TXREQUESCLKHS);
685
686 /* enables the DPI Video mode transmission */
687 dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
688 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, EN_CMD_MODE, 0);
689 dsi_update_bits(dsi, DSI_VID_MODE_CFG, EN_VIDEO_MODE, EN_VIDEO_MODE);
690 dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
691
692 printf("final DSI-Link bandwidth: %lu x %d Mbps\n",
693 dsi->phy.rate / USEC_PER_SEC, dsi->lanes);
694 }
695
rk618_dsi_disable(struct rk618_dsi * dsi)696 static void rk618_dsi_disable(struct rk618_dsi *dsi)
697 {
698 /* enables the Command mode protocol for transmissions */
699 dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
700 dsi_update_bits(dsi, DSI_PHY_IF_CTRL, PHY_TXREQUESCLKHS, 0);
701 dsi_update_bits(dsi, DSI_VID_MODE_CFG, EN_VIDEO_MODE, 0);
702 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, EN_CMD_MODE, EN_CMD_MODE);
703 dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, POWER_UP);
704 }
705
rk618_dsi_post_disable(struct rk618_dsi * dsi)706 static void rk618_dsi_post_disable(struct rk618_dsi *dsi)
707 {
708 dsi_update_bits(dsi, DSI_PWR_UP, SHUTDOWNZ, RESET);
709 dsi_update_bits(dsi, DSI_PHY_RSTZ, PHY_ENABLECLK, 0);
710
711 rk618_dsi_phy_power_off(dsi);
712 }
713
rk618_dsi_bridge_pre_enable(struct rockchip_bridge * bridge)714 static void rk618_dsi_bridge_pre_enable(struct rockchip_bridge *bridge)
715 {
716 struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
717
718 rk618_dsi_pre_enable(dsi);
719 }
720
rk618_dsi_bridge_enable(struct rockchip_bridge * bridge)721 static void rk618_dsi_bridge_enable(struct rockchip_bridge *bridge)
722 {
723 struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
724
725 rk618_dsi_enable(dsi);
726 }
727
rk618_dsi_bridge_post_disable(struct rockchip_bridge * bridge)728 static void rk618_dsi_bridge_post_disable(struct rockchip_bridge *bridge)
729 {
730 struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
731
732 rk618_dsi_post_disable(dsi);
733 }
734
rk618_dsi_bridge_disable(struct rockchip_bridge * bridge)735 static void rk618_dsi_bridge_disable(struct rockchip_bridge *bridge)
736 {
737 struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
738
739 rk618_dsi_disable(dsi);
740 }
741
rk618_dsi_bridge_mode_set(struct rockchip_bridge * bridge,const struct drm_display_mode * mode)742 static void rk618_dsi_bridge_mode_set(struct rockchip_bridge *bridge,
743 const struct drm_display_mode *mode)
744 {
745 struct rk618_dsi *dsi = dev_get_priv(bridge->dev);
746
747 memcpy(&dsi->mode, mode, sizeof(*mode));
748 }
749
750 static const struct rockchip_bridge_funcs rk618_dsi_bridge_funcs = {
751 .enable = rk618_dsi_bridge_enable,
752 .disable = rk618_dsi_bridge_disable,
753 .pre_enable = rk618_dsi_bridge_pre_enable,
754 .post_disable = rk618_dsi_bridge_post_disable,
755 .mode_set = rk618_dsi_bridge_mode_set,
756 };
757
rk618_dsi_transfer(struct rk618_dsi * dsi,const struct mipi_dsi_msg * msg)758 static ssize_t rk618_dsi_transfer(struct rk618_dsi *dsi,
759 const struct mipi_dsi_msg *msg)
760 {
761 struct mipi_dsi_packet packet;
762 u32 value, mask;
763 int ret;
764
765 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
766 dsi_update_bits(dsi, DSI_PHY_IF_CTRL, PHY_TXREQUESCLKHS, 0);
767 else
768 dsi_update_bits(dsi, DSI_PHY_IF_CTRL,
769 PHY_TXREQUESCLKHS, PHY_TXREQUESCLKHS);
770
771 switch (msg->type) {
772 case MIPI_DSI_DCS_SHORT_WRITE:
773 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_0P_TX,
774 msg->flags & MIPI_DSI_MSG_USE_LPM ?
775 DCS_SW_0P_TX : 0);
776 break;
777 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
778 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SW_1P_TX,
779 msg->flags & MIPI_DSI_MSG_USE_LPM ?
780 DCS_SW_1P_TX : 0);
781 break;
782 case MIPI_DSI_DCS_LONG_WRITE:
783 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_LW_TX,
784 msg->flags & MIPI_DSI_MSG_USE_LPM ?
785 DCS_LW_TX : 0);
786 break;
787 case MIPI_DSI_DCS_READ:
788 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, DCS_SR_0P_TX,
789 msg->flags & MIPI_DSI_MSG_USE_LPM ?
790 DCS_SR_0P_TX : 0);
791 break;
792 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
793 dsi_update_bits(dsi, DSI_CMD_MODE_CFG,
794 MAX_RD_PKT_SIZE,
795 msg->flags & MIPI_DSI_MSG_USE_LPM ?
796 MAX_RD_PKT_SIZE : 0);
797 break;
798 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
799 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_0P_TX,
800 msg->flags & MIPI_DSI_MSG_USE_LPM ?
801 GEN_SW_0P_TX : 0);
802 break;
803 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
804 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_1P_TX,
805 msg->flags & MIPI_DSI_MSG_USE_LPM ?
806 GEN_SW_1P_TX : 0);
807 break;
808 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
809 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SW_2P_TX,
810 msg->flags & MIPI_DSI_MSG_USE_LPM ?
811 GEN_SW_2P_TX : 0);
812 break;
813 case MIPI_DSI_GENERIC_LONG_WRITE:
814 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_LW_TX,
815 msg->flags & MIPI_DSI_MSG_USE_LPM ?
816 GEN_LW_TX : 0);
817 break;
818 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
819 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_0P_TX,
820 msg->flags & MIPI_DSI_MSG_USE_LPM ?
821 GEN_SR_0P_TX : 0);
822 break;
823 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
824 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_1P_TX,
825 msg->flags & MIPI_DSI_MSG_USE_LPM ?
826 GEN_SR_1P_TX : 0);
827 break;
828 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
829 dsi_update_bits(dsi, DSI_CMD_MODE_CFG, GEN_SR_2P_TX,
830 msg->flags & MIPI_DSI_MSG_USE_LPM ?
831 GEN_SR_2P_TX : 0);
832 break;
833 default:
834 return -EINVAL;
835 }
836
837 /* create a packet to the DSI protocol */
838 ret = mipi_dsi_create_packet(&packet, msg);
839 if (ret) {
840 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
841 return ret;
842 }
843
844 /* Send payload */
845 while (packet.payload_length >= 4) {
846 mask = GEN_PLD_W_FULL;
847 ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
848 value, !(value & mask), 50, 1000);
849 if (ret) {
850 dev_err(dsi->dev, "Write payload FIFO is full\n");
851 return ret;
852 }
853
854 value = get_unaligned_le32(packet.payload);
855 dsi_write(dsi, DSI_GEN_PLD_DATA, value);
856 packet.payload += 4;
857 packet.payload_length -= 4;
858 }
859
860 value = 0;
861 switch (packet.payload_length) {
862 case 3:
863 value |= packet.payload[2] << 16;
864 /* Fall through */
865 case 2:
866 value |= packet.payload[1] << 8;
867 /* Fall through */
868 case 1:
869 value |= packet.payload[0];
870 dsi_write(dsi, DSI_GEN_PLD_DATA, value);
871 break;
872 }
873
874 mask = GEN_CMD_FULL;
875 ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
876 value, !(value & mask), 50, 1000);
877 if (ret) {
878 dev_err(dsi->dev, "Command FIFO is full\n");
879 return ret;
880 }
881
882 /* Send packet header */
883 value = get_unaligned_le32(packet.header);
884 dsi_write(dsi, DSI_GEN_HDR, value);
885
886 mask = GEN_PLD_W_EMPTY | GEN_CMD_EMPTY;
887 ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
888 value, (value & mask) == mask, 50, 1000);
889 if (ret) {
890 dev_err(dsi->dev, "Write payload FIFO is not empty\n");
891 return ret;
892 }
893
894 if (msg->rx_len) {
895 u8 *payload = msg->rx_buf;
896 u16 length;
897
898 mask = GEN_RD_CMD_BUSY;
899 ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
900 value, !(value & mask), 50, 1000);
901 if (ret) {
902 dev_err(dsi->dev,
903 "entire response is not stored in the FIFO\n");
904 return ret;
905 }
906
907 /* Receive payload */
908 for (length = msg->rx_len; length; length -= 4) {
909 mask = GEN_PLD_R_EMPTY;
910 ret = dsi_read_poll_timeout(dsi, DSI_GEN_PKT_STATUS,
911 value, !(value & mask),
912 50, 1000);
913 if (ret) {
914 dev_err(dsi->dev,
915 "Read payload FIFO is empty\n");
916 return ret;
917 }
918
919 value = dsi_read(dsi, DSI_GEN_PLD_DATA);
920
921 switch (length) {
922 case 3:
923 payload[2] = (value >> 16) & 0xff;
924 /* Fall through */
925 case 2:
926 payload[1] = (value >> 8) & 0xff;
927 /* Fall through */
928 case 1:
929 payload[0] = value & 0xff;
930 return length;
931 }
932
933 payload[0] = (value >> 0) & 0xff;
934 payload[1] = (value >> 8) & 0xff;
935 payload[2] = (value >> 16) & 0xff;
936 payload[3] = (value >> 24) & 0xff;
937 payload += 4;
938 }
939 }
940
941 return packet.payload_length;
942 }
943
rk618_dsi_probe(struct udevice * dev)944 static int rk618_dsi_probe(struct udevice *dev)
945 {
946 struct rk618_dsi *dsi = dev_get_priv(dev);
947 struct rockchip_bridge *bridge =
948 (struct rockchip_bridge *)dev_get_driver_data(dev);
949 int ret;
950
951 dsi->dev = dev;
952 dsi->parent = dev_get_priv(dev->parent);
953
954 ret = device_probe(dev->parent);
955 if (ret)
956 return ret;
957
958 bridge->dev = dev;
959
960 /* Mask all interrupts */
961 dsi_write(dsi, DSI_INT_MSK0, 0xffffffff);
962 dsi_write(dsi, DSI_INT_MSK1, 0xffffffff);
963
964 return 0;
965 }
966
967 static struct rockchip_bridge rk618_dsi_driver_data = {
968 .funcs = &rk618_dsi_bridge_funcs,
969 };
970
971 static const struct udevice_id rk618_dsi_ids[] = {
972 {
973 .compatible = "rockchip,rk618-dsi",
974 .data = (ulong)&rk618_dsi_driver_data,
975 },
976 {}
977 };
978
rk618_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)979 static ssize_t rk618_dsi_host_transfer(struct mipi_dsi_host *host,
980 const struct mipi_dsi_msg *msg)
981 {
982 struct rk618_dsi *dsi = dev_get_priv(host->dev);
983
984 return rk618_dsi_transfer(dsi, msg);
985 }
986
rk618_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)987 static int rk618_dsi_host_attach(struct mipi_dsi_host *host,
988 struct mipi_dsi_device *device)
989 {
990 struct rk618_dsi *dsi = dev_get_priv(host->dev);
991
992 if (device->lanes < 1 || device->lanes > 4)
993 return -EINVAL;
994
995 dsi->lanes = device->lanes;
996 dsi->channel = device->channel;
997 dsi->format = device->format;
998 dsi->mode_flags = device->mode_flags;
999
1000 return 0;
1001 }
1002
1003 static const struct mipi_dsi_host_ops rk618_dsi_host_ops = {
1004 .attach = rk618_dsi_host_attach,
1005 .transfer = rk618_dsi_host_transfer,
1006 };
1007
rk618_dsi_bind(struct udevice * dev)1008 static int rk618_dsi_bind(struct udevice *dev)
1009 {
1010 struct mipi_dsi_host *host = dev_get_platdata(dev);
1011
1012 host->dev = dev;
1013 host->ops = &rk618_dsi_host_ops;
1014
1015 return dm_scan_fdt_dev(dev);
1016 }
1017
rk618_dsi_child_post_bind(struct udevice * dev)1018 static int rk618_dsi_child_post_bind(struct udevice *dev)
1019 {
1020 struct mipi_dsi_host *host = dev_get_platdata(dev->parent);
1021 struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
1022 char name[20];
1023
1024 sprintf(name, "%s.%d", host->dev->name, device->channel);
1025 device_set_name(dev, name);
1026
1027 device->dev = dev;
1028 device->host = host;
1029 device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
1030 device->format = dev_read_u32_default(dev, "dsi,format",
1031 MIPI_DSI_FMT_RGB888);
1032 device->mode_flags = dev_read_u32_default(dev, "dsi,flags",
1033 MIPI_DSI_MODE_VIDEO |
1034 MIPI_DSI_MODE_VIDEO_BURST |
1035 MIPI_DSI_MODE_VIDEO_HBP |
1036 MIPI_DSI_MODE_LPM |
1037 MIPI_DSI_MODE_EOT_PACKET);
1038 device->channel = dev_read_u32_default(dev, "reg", 0);
1039
1040 return 0;
1041 }
1042
rk618_dsi_child_pre_probe(struct udevice * dev)1043 static int rk618_dsi_child_pre_probe(struct udevice *dev)
1044 {
1045 struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
1046 int ret;
1047
1048 ret = mipi_dsi_attach(device);
1049 if (ret) {
1050 dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
1051 return ret;
1052 }
1053
1054 return 0;
1055 }
1056
1057 U_BOOT_DRIVER(rk618_dsi) = {
1058 .name = "rk618_dsi",
1059 .id = UCLASS_VIDEO_BRIDGE,
1060 .of_match = rk618_dsi_ids,
1061 .probe = rk618_dsi_probe,
1062 .bind = rk618_dsi_bind,
1063 .priv_auto_alloc_size = sizeof(struct rk618_dsi),
1064 .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
1065 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host),
1066 .child_post_bind = rk618_dsi_child_post_bind,
1067 .child_pre_probe = rk618_dsi_child_pre_probe,
1068 };
1069