1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <dm.h>
8*4882a593Smuzhiyun #include <errno.h>
9*4882a593Smuzhiyun #include <i2c.h>
10*4882a593Smuzhiyun #include <dm/pinctrl.h>
11*4882a593Smuzhiyun #include <dm/uclass.h>
12*4882a593Smuzhiyun #include <dm/uclass-id.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "rk1000.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define CTRL_ADC 0x00
17*4882a593Smuzhiyun #define ADC_OFF 0x88
18*4882a593Smuzhiyun #define CTRL_CODEC 0x01
19*4882a593Smuzhiyun #define CODEC_OFF 0x0d
20*4882a593Smuzhiyun #define CTRL_I2C 0x02
21*4882a593Smuzhiyun #define I2C_TIMEOUT_PERIOD 0x22
22*4882a593Smuzhiyun #define CTRL_TVE 0x03
23*4882a593Smuzhiyun #define TVE_OFF 0x00
24*4882a593Smuzhiyun
rk1000_ctl_i2c_write(struct rk1000_ctl * rk1000_ctl,u8 reg,u8 val)25*4882a593Smuzhiyun int rk1000_ctl_i2c_write(struct rk1000_ctl *rk1000_ctl, u8 reg, u8 val)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun struct dm_i2c_chip *chip = dev_get_parent_platdata(rk1000_ctl->dev);
28*4882a593Smuzhiyun struct i2c_msg msg;
29*4882a593Smuzhiyun u8 buf[2];
30*4882a593Smuzhiyun int ret;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun buf[0] = reg;
33*4882a593Smuzhiyun buf[1] = val;
34*4882a593Smuzhiyun msg.addr = chip->chip_addr;
35*4882a593Smuzhiyun msg.flags = 0;
36*4882a593Smuzhiyun msg.len = 2;
37*4882a593Smuzhiyun msg.buf = buf;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun ret = dm_i2c_xfer(rk1000_ctl->dev, &msg, 1);
40*4882a593Smuzhiyun if (ret) {
41*4882a593Smuzhiyun dev_err(rk1000_ctl->dev, "rk1000 ctrl i2c write failed: %d\n",
42*4882a593Smuzhiyun ret);
43*4882a593Smuzhiyun return ret;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
rk1000_ctl_i2c_read(struct rk1000_ctl * rk1000_ctl,u8 reg,u8 * val)49*4882a593Smuzhiyun int rk1000_ctl_i2c_read(struct rk1000_ctl *rk1000_ctl, u8 reg, u8 *val)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct dm_i2c_chip *chip = dev_get_parent_platdata(rk1000_ctl->dev);
52*4882a593Smuzhiyun u8 data;
53*4882a593Smuzhiyun struct i2c_msg msg[] = {
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun .addr = chip->chip_addr,
56*4882a593Smuzhiyun .flags = 0,
57*4882a593Smuzhiyun .buf = (u8 *)®,
58*4882a593Smuzhiyun .len = 1,
59*4882a593Smuzhiyun }, {
60*4882a593Smuzhiyun .addr = chip->chip_addr,
61*4882a593Smuzhiyun .flags = I2C_M_RD,
62*4882a593Smuzhiyun .buf = (u8 *)&data,
63*4882a593Smuzhiyun .len = 1,
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun int ret;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ret = dm_i2c_xfer(rk1000_ctl->dev, msg, 2);
69*4882a593Smuzhiyun if (ret) {
70*4882a593Smuzhiyun dev_err(rk1000_ctl->dev, "rk1000 ctrl i2c read failed: %d\n",
71*4882a593Smuzhiyun ret);
72*4882a593Smuzhiyun return ret;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun *val = data;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
rk1000_ctl_write_block(struct rk1000_ctl * rk1000_ctl,u8 reg,const u8 * buf,u8 len)80*4882a593Smuzhiyun int rk1000_ctl_write_block(struct rk1000_ctl *rk1000_ctl,
81*4882a593Smuzhiyun u8 reg, const u8 *buf, u8 len)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun int i, ret;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun for (i = 0; i < len; i++) {
86*4882a593Smuzhiyun ret = rk1000_ctl_i2c_write(rk1000_ctl, reg + i, buf[i]);
87*4882a593Smuzhiyun if (ret)
88*4882a593Smuzhiyun break;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return ret;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
rk1000_ctl_probe(struct udevice * dev)94*4882a593Smuzhiyun static int rk1000_ctl_probe(struct udevice *dev)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct rk1000_ctl *rk1000_ctl = dev_get_priv(dev);
97*4882a593Smuzhiyun int ret;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun rk1000_ctl->dev = dev;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun ret = gpio_request_by_name(dev, "reset-gpios", 0,
102*4882a593Smuzhiyun &rk1000_ctl->reset_gpio, GPIOD_IS_OUT);
103*4882a593Smuzhiyun if (ret) {
104*4882a593Smuzhiyun dev_err(dev, "Cannot get reset GPIO: %d\n", ret);
105*4882a593Smuzhiyun return ret;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun ret = clk_get_by_name(dev, "mclk", &rk1000_ctl->mclk);
109*4882a593Smuzhiyun if (ret < 0) {
110*4882a593Smuzhiyun dev_err(dev, "failed to get clkin: %d\n", ret);
111*4882a593Smuzhiyun return ret;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun clk_enable(&rk1000_ctl->mclk);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun pinctrl_select_state(rk1000_ctl->dev, "default");
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun dm_gpio_set_value(&rk1000_ctl->reset_gpio, 0);
119*4882a593Smuzhiyun mdelay(1);
120*4882a593Smuzhiyun dm_gpio_set_value(&rk1000_ctl->reset_gpio, 1);
121*4882a593Smuzhiyun mdelay(1);
122*4882a593Smuzhiyun dm_gpio_set_value(&rk1000_ctl->reset_gpio, 0);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun static const struct udevice_id rk1000_ctl_of_match[] = {
128*4882a593Smuzhiyun { .compatible = "rockchip,rk1000-ctl" },
129*4882a593Smuzhiyun {}
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun U_BOOT_DRIVER(rk1000) = {
133*4882a593Smuzhiyun .name = "rk1000_ctl",
134*4882a593Smuzhiyun .id = UCLASS_I2C_GENERIC,
135*4882a593Smuzhiyun .of_match = rk1000_ctl_of_match,
136*4882a593Smuzhiyun .probe = rk1000_ctl_probe,
137*4882a593Smuzhiyun .bind = dm_scan_fdt_dev,
138*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct rk1000_ctl),
139*4882a593Smuzhiyun };
140