1 /*
2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <malloc.h>
9 #include <syscon.h>
10 #include <asm/gpio.h>
11 #include <asm/arch-rockchip/clock.h>
12 #include <asm/arch/vendor.h>
13 #include <edid.h>
14 #include <dm/device.h>
15 #include <dm/of_access.h>
16 #include <dm/ofnode.h>
17 #include <dm/read.h>
18 #include <linux/hdmi.h>
19 #include <linux/media-bus-format.h>
20 #include <linux/dw_hdmi.h>
21 #include <asm/io.h>
22 #include "rockchip_display.h"
23 #include "rockchip_crtc.h"
24 #include "rockchip_connector.h"
25 #include "dw_hdmi.h"
26 #include "rockchip_phy.h"
27
28 #define HDCP_PRIVATE_KEY_SIZE 280
29 #define HDCP_KEY_SHA_SIZE 20
30 #define HDMI_HDCP1X_ID 5
31 #define HDMI_EDID_BLOCK_LEN 128
32 /*
33 * Unless otherwise noted, entries in this table are 100% optimization.
34 * Values can be obtained from hdmi_compute_n() but that function is
35 * slow so we pre-compute values we expect to see.
36 *
37 * All 32k and 48k values are expected to be the same (due to the way
38 * the math works) for any rate that's an exact kHz.
39 */
40 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
41 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
42 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
43 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
44 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
45 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
46 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
47 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
48 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
49 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
50 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
51 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
52 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
53 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
54 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
55 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
56 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
57 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
58 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
59 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
60 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
61 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
62 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
63 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
64 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
65 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
66 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
67 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
68 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
69 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
70 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
71 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
72 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
73 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
74 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
75 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
76 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
77 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
78
79 /* For 297 MHz+ HDMI spec have some other rule for setting N */
80 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
81 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
82
83 /* End of table */
84 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
85 };
86
87 static const u16 csc_coeff_default[3][4] = {
88 { 0x2000, 0x0000, 0x0000, 0x0000 },
89 { 0x0000, 0x2000, 0x0000, 0x0000 },
90 { 0x0000, 0x0000, 0x2000, 0x0000 }
91 };
92
93 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
94 { 0x2000, 0x6926, 0x74fd, 0x010e },
95 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
96 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
97 };
98
99 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
100 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
101 { 0x2000, 0x3264, 0x0000, 0x7e6d },
102 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
103 };
104
105 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
106 { 0x2591, 0x1322, 0x074b, 0x0000 },
107 { 0x6535, 0x2000, 0x7acc, 0x0200 },
108 { 0x6acd, 0x7534, 0x2000, 0x0200 }
109 };
110
111 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
112 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
113 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
114 { 0x6756, 0x78ab, 0x2000, 0x0200 }
115 };
116
117 static const u16 csc_coeff_full_to_limited[3][4] = {
118 { 0x36f7, 0x0000, 0x0000, 0x0040 },
119 { 0x0000, 0x36f7, 0x0000, 0x0040 },
120 { 0x0000, 0x0000, 0x36f7, 0x0040 }
121 };
122
123 struct hdmi_vmode {
124 bool mdataenablepolarity;
125
126 unsigned int mpixelclock;
127 unsigned int mpixelrepetitioninput;
128 unsigned int mpixelrepetitionoutput;
129 unsigned int mtmdsclock;
130 };
131
132 struct hdmi_data_info {
133 unsigned int enc_in_bus_format;
134 unsigned int enc_out_bus_format;
135 unsigned int enc_in_encoding;
136 unsigned int enc_out_encoding;
137 unsigned int quant_range;
138 unsigned int pix_repet_factor;
139 struct hdmi_vmode video_mode;
140 };
141
142 struct dw_hdmi_phy_data {
143 enum dw_hdmi_phy_type type;
144 const char *name;
145 unsigned int gen;
146 bool has_svsret;
147 int (*configure)(struct dw_hdmi *hdmi,
148 const struct dw_hdmi_plat_data *pdata,
149 unsigned long mpixelclock);
150 };
151
152 struct hdcp_keys {
153 u8 KSV[8];
154 u8 devicekey[HDCP_PRIVATE_KEY_SIZE];
155 u8 sha1[HDCP_KEY_SHA_SIZE];
156 u8 seeds[2];
157 };
158
159 struct dw_hdmi_i2c {
160 u8 slave_reg;
161 bool is_regaddr;
162 bool is_segment;
163
164 unsigned int scl_high_ns;
165 unsigned int scl_low_ns;
166 };
167
168 struct dw_hdmi {
169 int id;
170 enum dw_hdmi_devtype dev_type;
171 unsigned int version;
172 struct hdmi_data_info hdmi_data;
173 struct hdmi_edid_data edid_data;
174 const struct dw_hdmi_plat_data *plat_data;
175 struct ddc_adapter adap;
176
177 int vic;
178 int io_width;
179
180 unsigned long bus_format;
181 bool cable_plugin;
182 bool sink_is_hdmi;
183 bool sink_has_audio;
184 void *regs;
185 void *grf;
186 void *gpio_base;
187 struct dw_hdmi_i2c *i2c;
188
189 struct {
190 const struct dw_hdmi_phy_ops *ops;
191 const char *name;
192 void *data;
193 bool enabled;
194 } phy;
195
196 struct drm_display_mode previous_mode;
197
198 unsigned int sample_rate;
199 unsigned int audio_cts;
200 unsigned int audio_n;
201 bool audio_enable;
202 bool scramble_low_rates;
203
204 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
205 u8 (*read)(struct dw_hdmi *hdmi, int offset);
206
207 bool hdcp1x_enable;
208 bool output_bus_format_rgb;
209
210 struct gpio_desc hpd_gpiod;
211 };
212
dw_hdmi_writel(struct dw_hdmi * hdmi,u8 val,int offset)213 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
214 {
215 writel(val, hdmi->regs + (offset << 2));
216 }
217
dw_hdmi_readl(struct dw_hdmi * hdmi,int offset)218 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
219 {
220 return readl(hdmi->regs + (offset << 2));
221 }
222
dw_hdmi_writeb(struct dw_hdmi * hdmi,u8 val,int offset)223 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
224 {
225 writeb(val, hdmi->regs + offset);
226 }
227
dw_hdmi_readb(struct dw_hdmi * hdmi,int offset)228 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
229 {
230 return readb(hdmi->regs + offset);
231 }
232
hdmi_writeb(struct dw_hdmi * hdmi,u8 val,int offset)233 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
234 {
235 hdmi->write(hdmi, val, offset);
236 }
237
hdmi_readb(struct dw_hdmi * hdmi,int offset)238 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
239 {
240 return hdmi->read(hdmi, offset);
241 }
242
hdmi_modb(struct dw_hdmi * hdmi,u8 data,u8 mask,unsigned reg)243 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
244 {
245 u8 val = hdmi_readb(hdmi, reg) & ~mask;
246
247 val |= data & mask;
248 hdmi_writeb(hdmi, val, reg);
249 }
250
hdmi_mask_writeb(struct dw_hdmi * hdmi,u8 data,unsigned int reg,u8 shift,u8 mask)251 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
252 u8 shift, u8 mask)
253 {
254 hdmi_modb(hdmi, data << shift, mask, reg);
255 }
256
hdmi_bus_fmt_is_rgb(unsigned int bus_format)257 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
258 {
259 switch (bus_format) {
260 case MEDIA_BUS_FMT_RGB888_1X24:
261 case MEDIA_BUS_FMT_RGB101010_1X30:
262 case MEDIA_BUS_FMT_RGB121212_1X36:
263 case MEDIA_BUS_FMT_RGB161616_1X48:
264 return true;
265
266 default:
267 return false;
268 }
269 }
270
hdmi_bus_fmt_is_yuv444(unsigned int bus_format)271 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
272 {
273 switch (bus_format) {
274 case MEDIA_BUS_FMT_YUV8_1X24:
275 case MEDIA_BUS_FMT_YUV10_1X30:
276 case MEDIA_BUS_FMT_YUV12_1X36:
277 case MEDIA_BUS_FMT_YUV16_1X48:
278 return true;
279
280 default:
281 return false;
282 }
283 }
284
hdmi_bus_fmt_is_yuv422(unsigned int bus_format)285 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
286 {
287 switch (bus_format) {
288 case MEDIA_BUS_FMT_UYVY8_1X16:
289 case MEDIA_BUS_FMT_UYVY10_1X20:
290 case MEDIA_BUS_FMT_UYVY12_1X24:
291 return true;
292
293 default:
294 return false;
295 }
296 }
297
hdmi_bus_fmt_is_yuv420(unsigned int bus_format)298 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
299 {
300 switch (bus_format) {
301 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
302 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
303 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
304 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
305 return true;
306
307 default:
308 return false;
309 }
310 }
311
hdmi_bus_fmt_color_depth(unsigned int bus_format)312 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
313 {
314 switch (bus_format) {
315 case MEDIA_BUS_FMT_RGB888_1X24:
316 case MEDIA_BUS_FMT_YUV8_1X24:
317 case MEDIA_BUS_FMT_UYVY8_1X16:
318 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
319 return 8;
320
321 case MEDIA_BUS_FMT_RGB101010_1X30:
322 case MEDIA_BUS_FMT_YUV10_1X30:
323 case MEDIA_BUS_FMT_UYVY10_1X20:
324 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
325 return 10;
326
327 case MEDIA_BUS_FMT_RGB121212_1X36:
328 case MEDIA_BUS_FMT_YUV12_1X36:
329 case MEDIA_BUS_FMT_UYVY12_1X24:
330 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
331 return 12;
332
333 case MEDIA_BUS_FMT_RGB161616_1X48:
334 case MEDIA_BUS_FMT_YUV16_1X48:
335 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
336 return 16;
337
338 default:
339 return 0;
340 }
341 }
342
is_color_space_conversion(struct dw_hdmi * hdmi)343 static int is_color_space_conversion(struct dw_hdmi *hdmi)
344 {
345 struct drm_display_mode *mode =
346 hdmi->edid_data.preferred_mode;
347 bool is_cea_default;
348
349 is_cea_default = (drm_match_cea_mode(mode) > 1) &&
350 (hdmi->hdmi_data.quant_range ==
351 HDMI_QUANTIZATION_RANGE_DEFAULT);
352
353 /*
354 * When output is rgb limited range or default range with
355 * cea mode, csc should be enabled.
356 */
357 if (hdmi->hdmi_data.enc_in_bus_format !=
358 hdmi->hdmi_data.enc_out_bus_format ||
359 ((hdmi->hdmi_data.quant_range == HDMI_QUANTIZATION_RANGE_LIMITED ||
360 is_cea_default) &&
361 hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format)))
362 return 1;
363
364 return 0;
365 }
366
is_color_space_decimation(struct dw_hdmi * hdmi)367 static int is_color_space_decimation(struct dw_hdmi *hdmi)
368 {
369 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
370 return 0;
371
372 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
373 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
374 return 1;
375
376 return 0;
377 }
378
hdmi_phy_test_clear(struct dw_hdmi * hdmi,unsigned char bit)379 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
380 unsigned char bit)
381 {
382 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
383 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
384 }
385
hdmi_phy_test_enable(struct dw_hdmi * hdmi,unsigned char bit)386 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
387 unsigned char bit)
388 {
389 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
390 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
391 }
392
hdmi_phy_test_clock(struct dw_hdmi * hdmi,unsigned char bit)393 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
394 unsigned char bit)
395 {
396 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
397 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
398 }
399
hdmi_phy_test_din(struct dw_hdmi * hdmi,unsigned char bit)400 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
401 unsigned char bit)
402 {
403 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
404 }
405
hdmi_phy_test_dout(struct dw_hdmi * hdmi,unsigned char bit)406 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
407 unsigned char bit)
408 {
409 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
410 }
411
dw_hdmi_i2c_read(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)412 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
413 unsigned char *buf, unsigned int length)
414 {
415 struct dw_hdmi_i2c *i2c = hdmi->i2c;
416 int interrupt = 0, i = 20;
417 bool read_edid = false;
418
419 if (!i2c->is_regaddr) {
420 printf("set read register address to 0\n");
421 i2c->slave_reg = 0x00;
422 i2c->is_regaddr = true;
423 }
424
425 /* edid reads are in 128 bytes. scdc reads are in 1 byte */
426 if (length == HDMI_EDID_BLOCK_LEN)
427 read_edid = true;
428
429 while (length > 0) {
430 hdmi_writeb(hdmi, i2c->slave_reg, HDMI_I2CM_ADDRESS);
431
432 if (read_edid) {
433 i2c->slave_reg += 8;
434 length -= 8;
435 } else {
436 i2c->slave_reg++;
437 length--;
438 }
439
440 if (i2c->is_segment) {
441 if (read_edid)
442 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT,
443 HDMI_I2CM_OPERATION);
444 else
445 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
446 HDMI_I2CM_OPERATION);
447 } else {
448 if (read_edid)
449 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8,
450 HDMI_I2CM_OPERATION);
451 else
452 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
453 HDMI_I2CM_OPERATION);
454 }
455
456 while (i--) {
457 udelay(1000);
458 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
459 if (interrupt)
460 hdmi_writeb(hdmi, interrupt,
461 HDMI_IH_I2CM_STAT0);
462 if (interrupt & (m_SCDC_READREQ | m_I2CM_DONE |
463 m_I2CM_ERROR))
464 break;
465 }
466
467 if (!interrupt) {
468 printf("[%s] i2c read reg[0x%02x] no interrupt\n",
469 __func__, i2c->slave_reg);
470 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
471 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
472 HDMI_I2CM_OPERATION);
473 udelay(1000);
474 return -EAGAIN;
475 }
476
477 /* Check for error condition on the bus */
478 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) {
479 printf("[%s] read reg[0x%02x] data error:0x%02x\n",
480 __func__, i2c->slave_reg, interrupt);
481 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
482 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
483 HDMI_I2CM_OPERATION);
484 udelay(1000);
485 return -EIO;
486 }
487
488 i = 20;
489 if (read_edid)
490 for (i = 0; i < 8; i++)
491 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_READ_BUFF0 + i);
492 else
493 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
494 }
495 i2c->is_segment = false;
496
497 return 0;
498 }
499
dw_hdmi_i2c_write(struct dw_hdmi * hdmi,unsigned char * buf,unsigned int length)500 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
501 unsigned char *buf, unsigned int length)
502 {
503 struct dw_hdmi_i2c *i2c = hdmi->i2c;
504 int i = 20;
505 u8 interrupt = 0;
506
507 if (!i2c->is_regaddr) {
508 /* Use the first write byte as register address */
509 i2c->slave_reg = buf[0];
510 length--;
511 buf++;
512 i2c->is_regaddr = true;
513 }
514
515 while (length--) {
516 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
517 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
518 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
519 HDMI_I2CM_OPERATION);
520
521 while (i--) {
522 udelay(1000);
523 interrupt = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
524 if (interrupt)
525 hdmi_writeb(hdmi,
526 interrupt, HDMI_IH_I2CM_STAT0);
527
528 if (interrupt & (m_SCDC_READREQ |
529 m_I2CM_DONE | m_I2CM_ERROR))
530 break;
531 }
532
533 if (!interrupt) {
534 printf("[%s] i2c write reg[0x%02x] no interrupt\n",
535 __func__, i2c->slave_reg);
536 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
537 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
538 HDMI_I2CM_OPERATION);
539 udelay(1000);
540 return -EAGAIN;
541 }
542
543 if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
544 printf("[%s] write data error\n", __func__);
545 hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
546 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
547 HDMI_I2CM_OPERATION);
548 udelay(1000);
549 return -EIO;
550 } else if (interrupt & m_I2CM_DONE) {
551 printf("[%s] write offset %02x success\n",
552 __func__, i2c->slave_reg);
553 return -EAGAIN;
554 }
555
556 i = 20;
557 }
558
559 return 0;
560 }
561
dw_hdmi_i2c_xfer(struct ddc_adapter * adap,struct i2c_msg * msgs,int num)562 static int dw_hdmi_i2c_xfer(struct ddc_adapter *adap,
563 struct i2c_msg *msgs, int num)
564 {
565 struct dw_hdmi *hdmi = container_of(adap, struct dw_hdmi, adap);
566 struct dw_hdmi_i2c *i2c = hdmi->i2c;
567 u8 addr = msgs[0].addr;
568 int i, ret = 0;
569
570 printf("xfer: num: %d, addr: %#x\n", num, addr);
571 for (i = 0; i < num; i++) {
572 if (msgs[i].len == 0) {
573 printf("unsupported transfer %d/%d, no data\n",
574 i + 1, num);
575 return -EOPNOTSUPP;
576 }
577 }
578
579 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
580
581 /* Set slave device address taken from the first I2C message */
582 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
583 addr = DDC_ADDR;
584 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
585
586 /* Set slave device register address on transfer */
587 i2c->is_regaddr = false;
588
589 /* Set segment pointer for I2C extended read mode operation */
590 i2c->is_segment = false;
591
592 for (i = 0; i < num; i++) {
593 debug("xfer: num: %d/%d, len: %d, flags: %#x\n",
594 i + 1, num, msgs[i].len, msgs[i].flags);
595 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
596 i2c->is_segment = true;
597 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
598 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
599 } else {
600 if (msgs[i].flags & I2C_M_RD)
601 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
602 msgs[i].len);
603 else
604 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
605 msgs[i].len);
606 }
607 if (ret < 0)
608 break;
609 }
610
611 if (!ret)
612 ret = num;
613
614 /* Mute DONE and ERROR interrupts */
615 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
616 HDMI_IH_MUTE_I2CM_STAT0);
617
618 return ret;
619 }
620
hdmi_phy_wait_i2c_done(struct dw_hdmi * hdmi,int msec)621 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
622 {
623 u32 val;
624
625 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
626 if (msec-- == 0)
627 return false;
628 udelay(1000);
629 }
630 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
631
632 return true;
633 }
634
dw_hdmi_phy_i2c_write(struct dw_hdmi * hdmi,unsigned short data,unsigned char addr)635 static void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
636 unsigned char addr)
637 {
638 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
639 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
640 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
641 HDMI_PHY_I2CM_DATAO_1_ADDR);
642 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
643 HDMI_PHY_I2CM_DATAO_0_ADDR);
644 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
645 HDMI_PHY_I2CM_OPERATION_ADDR);
646 hdmi_phy_wait_i2c_done(hdmi, 1000);
647 }
648
dw_hdmi_phy_enable_powerdown(struct dw_hdmi * hdmi,bool enable)649 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
650 {
651 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
652 HDMI_PHY_CONF0_PDZ_OFFSET,
653 HDMI_PHY_CONF0_PDZ_MASK);
654 }
655
dw_hdmi_phy_enable_tmds(struct dw_hdmi * hdmi,u8 enable)656 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
657 {
658 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
659 HDMI_PHY_CONF0_ENTMDS_OFFSET,
660 HDMI_PHY_CONF0_ENTMDS_MASK);
661 }
662
dw_hdmi_phy_enable_svsret(struct dw_hdmi * hdmi,u8 enable)663 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
664 {
665 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
666 HDMI_PHY_CONF0_SVSRET_OFFSET,
667 HDMI_PHY_CONF0_SVSRET_MASK);
668 }
669
dw_hdmi_phy_gen2_pddq(struct dw_hdmi * hdmi,u8 enable)670 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
671 {
672 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
673 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
674 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
675 }
676
dw_hdmi_phy_gen2_txpwron(struct dw_hdmi * hdmi,u8 enable)677 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
678 {
679 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
680 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
681 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
682 }
683
dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi * hdmi,u8 enable)684 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
685 {
686 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
687 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
688 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
689 }
690
dw_hdmi_phy_sel_interface_control(struct dw_hdmi * hdmi,u8 enable)691 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
692 {
693 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
694 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
695 HDMI_PHY_CONF0_SELDIPIF_MASK);
696 }
697
dw_hdmi_phy_power_off(struct dw_hdmi * hdmi)698 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
699 {
700 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
701 unsigned int i;
702 u16 val;
703
704 if (phy->gen == 1) {
705 dw_hdmi_phy_enable_tmds(hdmi, 0);
706 dw_hdmi_phy_enable_powerdown(hdmi, true);
707 return;
708 }
709
710 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
711
712 /*
713 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
714 * to low power mode.
715 */
716 for (i = 0; i < 5; ++i) {
717 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
718 if (!(val & HDMI_PHY_TX_PHY_LOCK))
719 break;
720
721 udelay(2000);
722 }
723
724 if (val & HDMI_PHY_TX_PHY_LOCK)
725 printf("PHY failed to power down\n");
726 else
727 printf("PHY powered down in %u iterations\n", i);
728
729 dw_hdmi_phy_gen2_pddq(hdmi, 1);
730 }
731
dw_hdmi_phy_power_on(struct dw_hdmi * hdmi)732 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
733 {
734 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
735 unsigned int i;
736 u8 val;
737
738 if (phy->gen == 1) {
739 dw_hdmi_phy_enable_powerdown(hdmi, false);
740
741 /* Toggle TMDS enable. */
742 dw_hdmi_phy_enable_tmds(hdmi, 0);
743 dw_hdmi_phy_enable_tmds(hdmi, 1);
744 return 0;
745 }
746
747 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
748 dw_hdmi_phy_gen2_pddq(hdmi, 0);
749
750 /* Wait for PHY PLL lock */
751 for (i = 0; i < 5; ++i) {
752 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
753 if (val)
754 break;
755
756 udelay(2000);
757 }
758
759 if (!val) {
760 printf("PHY PLL failed to lock\n");
761 return -ETIMEDOUT;
762 }
763 printf("PHY PLL locked %u iterations\n", i);
764
765 return 0;
766 }
767
768 /*
769 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
770 * information the DWC MHL PHY has the same register layout and is thus also
771 * supported by this function.
772 */
773 static
hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi * hdmi,const struct dw_hdmi_plat_data * pdata,unsigned long mpixelclock)774 int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
775 const struct dw_hdmi_plat_data *pdata,
776 unsigned long mpixelclock)
777 {
778 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
779 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
780 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
781 unsigned int tmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
782 unsigned int depth =
783 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
784
785 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) &&
786 pdata->mpll_cfg_420)
787 mpll_config = pdata->mpll_cfg_420;
788
789 /* PLL/MPLL Cfg - always match on final entry */
790 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
791 if (mpixelclock <= mpll_config->mpixelclock)
792 break;
793
794 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
795 if (tmdsclock <= curr_ctrl->mpixelclock)
796 break;
797
798 for (; phy_config->mpixelclock != ~0UL; phy_config++)
799 if (tmdsclock <= phy_config->mpixelclock)
800 break;
801
802 if (mpll_config->mpixelclock == ~0UL ||
803 curr_ctrl->mpixelclock == ~0UL ||
804 phy_config->mpixelclock == ~0UL)
805 return -EINVAL;
806
807 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
808 depth = fls(depth - 8);
809 else
810 depth = 0;
811 if (depth)
812 depth--;
813
814 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].cpce,
815 HDMI_3D_TX_PHY_CPCE_CTRL);
816
817 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[depth].gmp,
818 HDMI_3D_TX_PHY_GMPCTRL);
819 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[depth],
820 HDMI_3D_TX_PHY_CURRCTRL);
821
822 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
823 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
824 HDMI_3D_TX_PHY_MSM_CTRL);
825
826 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
827 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
828 HDMI_3D_TX_PHY_CKSYMTXCTRL);
829 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
830 HDMI_3D_TX_PHY_VLEVCTRL);
831
832 return 0;
833 }
834
835 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
836 {
837 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
838 .name = "DWC HDMI TX PHY",
839 .gen = 1,
840 }, {
841 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
842 .name = "DWC MHL PHY + HEAC PHY",
843 .gen = 2,
844 .has_svsret = true,
845 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
846 }, {
847 .type = DW_HDMI_PHY_DWC_MHL_PHY,
848 .name = "DWC MHL PHY",
849 .gen = 2,
850 .has_svsret = true,
851 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
852 }, {
853 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
854 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
855 .gen = 2,
856 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
857 }, {
858 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
859 .name = "DWC HDMI 3D TX PHY",
860 .gen = 2,
861 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
862 }, {
863 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
864 .name = "DWC HDMI 2.0 TX PHY",
865 .gen = 2,
866 .has_svsret = true,
867 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
868 }, {
869 .type = DW_HDMI_PHY_VENDOR_PHY,
870 .name = "Vendor PHY",
871 }
872 };
873
rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi * hdmi,int enable)874 static int rockchip_dw_hdmi_scrambling_enable(struct dw_hdmi *hdmi,
875 int enable)
876 {
877 u8 stat;
878
879 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat);
880
881 if (stat < 0) {
882 debug("Failed to read tmds config\n");
883 return false;
884 }
885
886 if (enable == 1) {
887 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
888 stat |= SCDC_SCRAMBLING_ENABLE;
889 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat);
890 /* TMDS software reset request */
891 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
892 HDMI_MC_SWRSTZ);
893 /* Enable/Disable Scrambling */
894 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
895 } else {
896 /* Enable/Disable Scrambling */
897 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
898 /* TMDS software reset request */
899 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
900 HDMI_MC_SWRSTZ);
901 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
902 stat &= ~SCDC_SCRAMBLING_ENABLE;
903 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat);
904 }
905
906 return 0;
907 }
908
rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi * hdmi)909 static void rockchip_dw_hdmi_scdc_set_tmds_rate(struct dw_hdmi *hdmi)
910 {
911 u8 stat;
912
913 drm_scdc_readb(&hdmi->adap, SCDC_TMDS_CONFIG, &stat);
914 if (hdmi->hdmi_data.video_mode.mtmdsclock > 340000000)
915 stat |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
916 else
917 stat &= ~SCDC_TMDS_BIT_CLOCK_RATIO_BY_40;
918 drm_scdc_writeb(&hdmi->adap, SCDC_TMDS_CONFIG, stat);
919 }
920
hdmi_phy_configure(struct dw_hdmi * hdmi)921 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
922 {
923 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
924 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
925 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
926 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
927 int ret;
928
929 dw_hdmi_phy_power_off(hdmi);
930
931 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
932 if (hdmi->edid_data.display_info.hdmi.scdc.supported)
933 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi);
934
935 /* Leave low power consumption mode by asserting SVSRET. */
936 if (phy->has_svsret)
937 dw_hdmi_phy_enable_svsret(hdmi, 1);
938
939 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
940 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
941 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
942
943 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
944
945 hdmi_phy_test_clear(hdmi, 1);
946 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
947 HDMI_PHY_I2CM_SLAVE_ADDR);
948 hdmi_phy_test_clear(hdmi, 0);
949
950 /* Write to the PHY as configured by the platform */
951 if (pdata->configure_phy)
952 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
953 else
954 ret = phy->configure(hdmi, pdata, mpixelclock);
955 if (ret) {
956 printf("PHY configuration failed (clock %lu)\n",
957 mpixelclock);
958 return ret;
959 }
960
961 /* Wait for resuming transmission of TMDS clock and data */
962 if (mtmdsclock > 340000000)
963 mdelay(100);
964
965 return dw_hdmi_phy_power_on(hdmi);
966 }
967
dw_hdmi_phy_init(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)968 static int dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi,
969 void *data)
970 {
971 int i, ret;
972
973 /* HDMI Phy spec says to do the phy initialization sequence twice */
974 for (i = 0; i < 2; i++) {
975 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
976 dw_hdmi_phy_sel_interface_control(hdmi, 0);
977 ret = hdmi_phy_configure(hdmi);
978 if (ret)
979 return ret;
980 }
981
982 return 0;
983 }
984
dw_hdmi_phy_disable(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)985 static void dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi,
986 void *data)
987 {
988 dw_hdmi_phy_power_off(hdmi);
989 }
990
991 static enum drm_connector_status
dw_hdmi_phy_read_hpd(struct dw_hdmi * hdmi,void * data)992 dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data)
993 {
994 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
995 connector_status_connected : connector_status_disconnected;
996 }
997
998 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
999 .init = dw_hdmi_phy_init,
1000 .disable = dw_hdmi_phy_disable,
1001 .read_hpd = dw_hdmi_phy_read_hpd,
1002 };
1003
dw_hdmi_detect_phy(struct dw_hdmi * hdmi)1004 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
1005 {
1006 unsigned int i;
1007 u8 phy_type;
1008
1009 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
1010
1011 /*
1012 * RK3228 and RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
1013 * but it has a vedor phy.
1014 */
1015 if (phy_type == DW_HDMI_PHY_VENDOR_PHY ||
1016 hdmi->dev_type == RK3528_HDMI ||
1017 hdmi->dev_type == RK3328_HDMI ||
1018 hdmi->dev_type == RK3228_HDMI) {
1019 /* Vendor PHYs require support from the glue layer. */
1020 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
1021 printf(
1022 "Vendor HDMI PHY not supported by glue layer\n");
1023 return -ENODEV;
1024 }
1025
1026 hdmi->phy.ops = hdmi->plat_data->phy_ops;
1027 hdmi->phy.data = hdmi->plat_data->phy_data;
1028 hdmi->phy.name = hdmi->plat_data->phy_name;
1029 return 0;
1030 }
1031
1032 /* Synopsys PHYs are handled internally. */
1033 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
1034 if (dw_hdmi_phys[i].type == phy_type) {
1035 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
1036 hdmi->phy.name = dw_hdmi_phys[i].name;
1037 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
1038
1039 if (!dw_hdmi_phys[i].configure &&
1040 !hdmi->plat_data->configure_phy) {
1041 printf("%s requires platform support\n",
1042 hdmi->phy.name);
1043 return -ENODEV;
1044 }
1045
1046 return 0;
1047 }
1048 }
1049
1050 printf("Unsupported HDMI PHY type (%02x)\n", phy_type);
1051 return -ENODEV;
1052 }
1053
1054 static unsigned int
hdmi_get_tmdsclock(struct dw_hdmi * hdmi,unsigned long mpixelclock)1055 hdmi_get_tmdsclock(struct dw_hdmi *hdmi, unsigned long mpixelclock)
1056 {
1057 unsigned int tmdsclock = mpixelclock;
1058 unsigned int depth =
1059 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
1060
1061 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1062 switch (depth) {
1063 case 16:
1064 tmdsclock = mpixelclock * 2;
1065 break;
1066 case 12:
1067 tmdsclock = mpixelclock * 3 / 2;
1068 break;
1069 case 10:
1070 tmdsclock = mpixelclock * 5 / 4;
1071 break;
1072 default:
1073 break;
1074 }
1075 }
1076
1077 return tmdsclock;
1078 }
1079
hdmi_av_composer(struct dw_hdmi * hdmi,const struct drm_display_mode * mode)1080 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1081 const struct drm_display_mode *mode)
1082 {
1083 u8 bytes = 0, inv_val = 0;
1084 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1085 struct drm_hdmi_info *hdmi_info = &hdmi->edid_data.display_info.hdmi;
1086 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1087 unsigned int hdisplay, vdisplay;
1088
1089 vmode->mpixelclock = mode->crtc_clock * 1000;
1090 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1091 DRM_MODE_FLAG_3D_FRAME_PACKING)
1092 vmode->mpixelclock *= 2;
1093 vmode->mtmdsclock = hdmi_get_tmdsclock(hdmi, vmode->mpixelclock);
1094 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1095 vmode->mtmdsclock /= 2;
1096 printf("final pixclk = %d tmdsclk = %d\n",
1097 vmode->mpixelclock, vmode->mtmdsclock);
1098
1099 /* Set up HDMI_FC_INVIDCONF
1100 * Some display equipments require that the interval
1101 * between Video Data and Data island must be at least 58 pixels,
1102 * and fc_invidconf.HDCP_keepout set (1'b1) can meet the requirement.
1103 */
1104 inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE;
1105
1106 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1107 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1108 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1109
1110 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1111 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1112 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1113
1114 inv_val |= (vmode->mdataenablepolarity ?
1115 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1116 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1117
1118 if (hdmi->vic == 39)
1119 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1120 else
1121 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1122 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1123 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1124
1125 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1126 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1127 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1128
1129 inv_val |= hdmi->sink_is_hdmi ?
1130 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1131 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1132
1133 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1134
1135 hdisplay = mode->hdisplay;
1136 hblank = mode->htotal - mode->hdisplay;
1137 h_de_hs = mode->hsync_start - mode->hdisplay;
1138 hsync_len = mode->hsync_end - mode->hsync_start;
1139
1140 /*
1141 * When we're setting a YCbCr420 mode, we need
1142 * to adjust the horizontal timing to suit.
1143 */
1144 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1145 hdisplay /= 2;
1146 hblank /= 2;
1147 h_de_hs /= 2;
1148 hsync_len /= 2;
1149 }
1150
1151 vdisplay = mode->vdisplay;
1152 vblank = mode->vtotal - mode->vdisplay;
1153 v_de_vs = mode->vsync_start - mode->vdisplay;
1154 vsync_len = mode->vsync_end - mode->vsync_start;
1155
1156 /*
1157 * When we're setting an interlaced mode, we need
1158 * to adjust the vertical timing to suit.
1159 */
1160 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1161 vdisplay /= 2;
1162 vblank /= 2;
1163 v_de_vs /= 2;
1164 vsync_len /= 2;
1165 } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1166 DRM_MODE_FLAG_3D_FRAME_PACKING) {
1167 vdisplay += mode->vtotal;
1168 }
1169
1170 /* Scrambling Control */
1171 if (hdmi_info->scdc.supported) {
1172 if (vmode->mtmdsclock > 340000000 ||
1173 (hdmi_info->scdc.scrambling.low_rates &&
1174 hdmi->scramble_low_rates)) {
1175 drm_scdc_readb(&hdmi->adap, SCDC_SINK_VERSION, &bytes);
1176 drm_scdc_writeb(&hdmi->adap, SCDC_SOURCE_VERSION,
1177 bytes);
1178 rockchip_dw_hdmi_scrambling_enable(hdmi, 1);
1179 } else {
1180 rockchip_dw_hdmi_scrambling_enable(hdmi, 0);
1181 }
1182 }
1183
1184 /* Set up horizontal active pixel width */
1185 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1186 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1187
1188 /* Set up vertical active lines */
1189 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1190 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1191
1192 /* Set up horizontal blanking pixel region width */
1193 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1194 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1195
1196 /* Set up vertical blanking pixel region width */
1197 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1198
1199 /* Set up HSYNC active edge delay width (in pixel clks) */
1200 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1201 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1202
1203 /* Set up VSYNC active edge delay (in lines) */
1204 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1205
1206 /* Set up HSYNC active pulse width (in pixel clks) */
1207 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1208 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1209
1210 /* Set up VSYNC active edge delay (in lines) */
1211 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1212 }
1213
dw_hdmi_update_csc_coeffs(struct dw_hdmi * hdmi)1214 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1215 {
1216 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1217 unsigned i;
1218 u32 csc_scale = 1;
1219 int enc_out_rgb, enc_in_rgb;
1220
1221 enc_out_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1222 enc_in_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1223
1224 if (is_color_space_conversion(hdmi)) {
1225 if (enc_out_rgb && enc_in_rgb) {
1226 csc_coeff = &csc_coeff_full_to_limited;
1227 csc_scale = 0;
1228 } else if (enc_out_rgb) {
1229 if (hdmi->hdmi_data.enc_out_encoding ==
1230 V4L2_YCBCR_ENC_601)
1231 csc_coeff = &csc_coeff_rgb_out_eitu601;
1232 else
1233 csc_coeff = &csc_coeff_rgb_out_eitu709;
1234 } else if (enc_in_rgb) {
1235 if (hdmi->hdmi_data.enc_out_encoding ==
1236 V4L2_YCBCR_ENC_601)
1237 csc_coeff = &csc_coeff_rgb_in_eitu601;
1238 else
1239 csc_coeff = &csc_coeff_rgb_in_eitu709;
1240 csc_scale = 0;
1241 }
1242 }
1243
1244 /* The CSC registers are sequential, alternating MSB then LSB */
1245 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1246 u16 coeff_a = (*csc_coeff)[0][i];
1247 u16 coeff_b = (*csc_coeff)[1][i];
1248 u16 coeff_c = (*csc_coeff)[2][i];
1249
1250 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1251 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1252 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1253 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1254 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1255 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1256 }
1257
1258 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1259 HDMI_CSC_SCALE);
1260 }
1261
is_color_space_interpolation(struct dw_hdmi * hdmi)1262 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
1263 {
1264 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1265 return 0;
1266
1267 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1268 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1269 return 1;
1270
1271 return 0;
1272 }
1273
hdmi_video_csc(struct dw_hdmi * hdmi)1274 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1275 {
1276 int color_depth = 0;
1277 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1278 int decimation = 0;
1279
1280 /* YCC422 interpolation to 444 mode */
1281 if (is_color_space_interpolation(hdmi))
1282 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1283 else if (is_color_space_decimation(hdmi))
1284 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1285
1286 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1287 case 8:
1288 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1289 break;
1290 case 10:
1291 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1292 break;
1293 case 12:
1294 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1295 break;
1296 case 16:
1297 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1298 break;
1299
1300 default:
1301 return;
1302 }
1303
1304 /* Configure the CSC registers */
1305 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1306 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1307 HDMI_CSC_SCALE);
1308
1309 dw_hdmi_update_csc_coeffs(hdmi);
1310 }
1311
dw_hdmi_enable_video_path(struct dw_hdmi * hdmi)1312 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1313 {
1314 u8 clkdis;
1315
1316 /* control period minimum duration */
1317 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1318 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1319 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1320
1321 /* Set to fill TMDS data channels */
1322 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1323 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1324 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1325
1326 /* Enable pixel clock and tmds data path */
1327 clkdis = 0x7F;
1328 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1329 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1330
1331 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1332 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1333
1334 /* Enable csc path */
1335 if (is_color_space_conversion(hdmi)) {
1336 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1337 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1338 }
1339
1340 /* Enable pixel repetition path */
1341 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1342 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1343 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1344 }
1345
1346 /* Enable color space conversion if needed */
1347 if (is_color_space_conversion(hdmi))
1348 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1349 HDMI_MC_FLOWCTRL);
1350 else
1351 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1352 HDMI_MC_FLOWCTRL);
1353 }
1354
dw_hdmi_clear_overflow(struct dw_hdmi * hdmi)1355 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1356 {
1357 unsigned int count;
1358 unsigned int i;
1359 u8 val;
1360
1361 /*
1362 * Under some circumstances the Frame Composer arithmetic unit can miss
1363 * an FC register write due to being busy processing the previous one.
1364 * The issue can be worked around by issuing a TMDS software reset and
1365 * then write one of the FC registers several times.
1366 *
1367 * The number of iterations matters and depends on the HDMI TX revision
1368 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1369 * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1370 * 4 and 1 iterations respectively.
1371 */
1372
1373 switch (hdmi->version) {
1374 case 0x130a:
1375 count = 4;
1376 break;
1377 case 0x131a:
1378 case 0x200a:
1379 case 0x201a:
1380 case 0x211a:
1381 count = 1;
1382 break;
1383 default:
1384 return;
1385 }
1386
1387 /* TMDS software reset */
1388 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1389
1390 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1391 for (i = 0; i < count; i++)
1392 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1393 }
1394
hdmi_disable_overflow_interrupts(struct dw_hdmi * hdmi)1395 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1396 {
1397 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1398 HDMI_IH_MUTE_FC_STAT2);
1399 }
1400
hdmi_video_packetize(struct dw_hdmi * hdmi)1401 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1402 {
1403 unsigned int color_depth = 0;
1404 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1405 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1406 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1407 u8 val, vp_conf;
1408
1409 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1410 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1411 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1412 switch (hdmi_bus_fmt_color_depth(
1413 hdmi->hdmi_data.enc_out_bus_format)) {
1414 case 8:
1415 color_depth = 0;
1416 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1417 break;
1418 case 10:
1419 color_depth = 5;
1420 break;
1421 case 12:
1422 color_depth = 6;
1423 break;
1424 case 16:
1425 color_depth = 7;
1426 break;
1427 default:
1428 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1429 }
1430 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1431 switch (hdmi_bus_fmt_color_depth(
1432 hdmi->hdmi_data.enc_out_bus_format)) {
1433 case 0:
1434 case 8:
1435 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1436 break;
1437 case 10:
1438 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1439 break;
1440 case 12:
1441 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1442 break;
1443
1444 default:
1445 return;
1446 }
1447 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1448 } else {
1449 return;
1450 }
1451
1452 /* set the packetizer registers */
1453 val = (color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1454 HDMI_VP_PR_CD_COLOR_DEPTH_MASK;
1455 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1456
1457 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1458 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1459
1460 /* Data from pixel repeater block */
1461 if (hdmi_data->pix_repet_factor > 0) {
1462 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1463 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1464 } else { /* data from packetizer block */
1465 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1466 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1467 }
1468
1469 hdmi_modb(hdmi, vp_conf,
1470 HDMI_VP_CONF_PR_EN_MASK |
1471 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1472
1473 hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
1474 HDMI_VP_STUFF);
1475
1476 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1477
1478 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1479 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1480 HDMI_VP_CONF_PP_EN_ENABLE |
1481 HDMI_VP_CONF_YCC422_EN_DISABLE;
1482 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1483 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1484 HDMI_VP_CONF_PP_EN_DISABLE |
1485 HDMI_VP_CONF_YCC422_EN_ENABLE;
1486 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1487 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1488 HDMI_VP_CONF_PP_EN_DISABLE |
1489 HDMI_VP_CONF_YCC422_EN_DISABLE;
1490 } else {
1491 return;
1492 }
1493
1494 hdmi_modb(hdmi, vp_conf,
1495 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1496 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1497
1498 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1499 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1500 HDMI_VP_STUFF_PP_STUFFING_MASK |
1501 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1502
1503 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1504 HDMI_VP_CONF);
1505 }
1506
hdmi_video_sample(struct dw_hdmi * hdmi)1507 static void hdmi_video_sample(struct dw_hdmi *hdmi)
1508 {
1509 int color_format = 0;
1510 u8 val;
1511
1512 switch (hdmi->hdmi_data.enc_in_bus_format) {
1513 case MEDIA_BUS_FMT_RGB888_1X24:
1514 color_format = 0x01;
1515 break;
1516 case MEDIA_BUS_FMT_RGB101010_1X30:
1517 color_format = 0x03;
1518 break;
1519 case MEDIA_BUS_FMT_RGB121212_1X36:
1520 color_format = 0x05;
1521 break;
1522 case MEDIA_BUS_FMT_RGB161616_1X48:
1523 color_format = 0x07;
1524 break;
1525
1526 case MEDIA_BUS_FMT_YUV8_1X24:
1527 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1528 color_format = 0x09;
1529 break;
1530 case MEDIA_BUS_FMT_YUV10_1X30:
1531 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1532 color_format = 0x0B;
1533 break;
1534 case MEDIA_BUS_FMT_YUV12_1X36:
1535 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
1536 color_format = 0x0D;
1537 break;
1538 case MEDIA_BUS_FMT_YUV16_1X48:
1539 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
1540 color_format = 0x0F;
1541 break;
1542
1543 case MEDIA_BUS_FMT_UYVY8_1X16:
1544 color_format = 0x16;
1545 break;
1546 case MEDIA_BUS_FMT_UYVY10_1X20:
1547 color_format = 0x14;
1548 break;
1549 case MEDIA_BUS_FMT_UYVY12_1X24:
1550 color_format = 0x12;
1551 break;
1552
1553 default:
1554 return;
1555 }
1556
1557 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
1558 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
1559 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
1560 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
1561
1562 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
1563 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
1564 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
1565 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
1566 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
1567 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
1568 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
1569 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
1570 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
1571 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
1572 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
1573 }
1574
dw_hdmi_disable(struct rockchip_connector * conn,struct dw_hdmi * hdmi,struct display_state * state)1575 static void dw_hdmi_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi,
1576 struct display_state *state)
1577 {
1578 if (hdmi->phy.enabled) {
1579 hdmi->phy.ops->disable(conn, hdmi, state);
1580 hdmi->phy.enabled = false;
1581 }
1582 }
1583
hdmi_config_AVI(struct dw_hdmi * hdmi,struct drm_display_mode * mode)1584 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1585 {
1586 struct hdmi_avi_infoframe frame;
1587 u8 val;
1588 bool is_hdmi2 = false;
1589 enum hdmi_quantization_range rgb_quant_range =
1590 hdmi->hdmi_data.quant_range;
1591
1592 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) ||
1593 hdmi->edid_data.display_info.hdmi.scdc.supported)
1594 is_hdmi2 = true;
1595 /* Initialise info frame from DRM mode */
1596 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
1597
1598 /*
1599 * Ignore monitor selectable quantization, use quantization set
1600 * by the user
1601 */
1602 drm_hdmi_avi_infoframe_quant_range(&frame, mode, rgb_quant_range,
1603 true);
1604 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1605 frame.colorspace = HDMI_COLORSPACE_YUV444;
1606 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1607 frame.colorspace = HDMI_COLORSPACE_YUV422;
1608 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1609 frame.colorspace = HDMI_COLORSPACE_YUV420;
1610 else
1611 frame.colorspace = HDMI_COLORSPACE_RGB;
1612
1613 /* Set up colorimetry */
1614 switch (hdmi->hdmi_data.enc_out_encoding) {
1615 case V4L2_YCBCR_ENC_601:
1616 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1617 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1618 else
1619 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1620 frame.extended_colorimetry =
1621 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1622 break;
1623 case V4L2_YCBCR_ENC_709:
1624 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1625 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1626 else
1627 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1628 frame.extended_colorimetry =
1629 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1630 break;
1631 default: /* Carries no data */
1632 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1633 frame.extended_colorimetry =
1634 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1635 break;
1636 }
1637
1638 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1639
1640 /*
1641 * The Designware IP uses a different byte format from standard
1642 * AVI info frames, though generally the bits are in the correct
1643 * bytes.
1644 */
1645
1646 /*
1647 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1648 * 5,6,7, active aspect present in bit 6 rather than 4.
1649 */
1650 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1651 if (frame.active_aspect & 15)
1652 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1653 if (frame.top_bar || frame.bottom_bar)
1654 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1655 if (frame.left_bar || frame.right_bar)
1656 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1657 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1658
1659 /* AVI data byte 2 differences: none */
1660 val = ((frame.colorimetry & 0x3) << 6) |
1661 ((frame.picture_aspect & 0x3) << 4) |
1662 (frame.active_aspect & 0xf);
1663 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1664
1665 /* AVI data byte 3 differences: none */
1666 val = ((frame.extended_colorimetry & 0x7) << 4) |
1667 ((frame.quantization_range & 0x3) << 2) |
1668 (frame.nups & 0x3);
1669 if (frame.itc)
1670 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1671 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1672
1673 /* AVI data byte 4 differences: none */
1674 val = frame.video_code & 0x7f;
1675 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1676
1677 /* AVI Data Byte 5- set up input and output pixel repetition */
1678 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1679 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1680 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1681 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1682 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1683 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1684 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1685
1686 /*
1687 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1688 * ycc range in bits 2,3 rather than 6,7
1689 */
1690 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1691 (frame.content_type & 0x3);
1692 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1693
1694 /* AVI Data Bytes 6-13 */
1695 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1696 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1697 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1698 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1699 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1700 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1701 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1702 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1703 }
1704
hdmi_config_vendor_specific_infoframe(struct dw_hdmi * hdmi,struct drm_display_mode * mode)1705 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1706 struct drm_display_mode *mode)
1707 {
1708 struct hdmi_vendor_infoframe frame;
1709 u8 buffer[10];
1710 ssize_t err;
1711
1712 /* Disable HDMI vendor specific infoframe send */
1713 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1714 HDMI_FC_DATAUTO0_VSD_MASK);
1715
1716 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1717 if (err < 0)
1718 /*
1719 * Going into that statement does not means vendor infoframe
1720 * fails. It just informed us that vendor infoframe is not
1721 * needed for the selected mode. Only 4k or stereoscopic 3D
1722 * mode requires vendor infoframe. So just simply return.
1723 */
1724 return;
1725
1726 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1727 if (err < 0) {
1728 printf("Failed to pack vendor infoframe: %zd\n", err);
1729 return;
1730 }
1731
1732 /* Set the length of HDMI vendor specific InfoFrame payload */
1733 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1734
1735 /* Set 24bit IEEE Registration Identifier */
1736 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1737 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1738 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1739
1740 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1741 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1742 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1743
1744 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1745 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1746
1747 /* Packet frame interpolation */
1748 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1749
1750 /* Auto packets per frame and line spacing */
1751 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1752
1753 /* Configures the Frame Composer On RDRB mode */
1754 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1755 HDMI_FC_DATAUTO0_VSD_MASK);
1756 }
1757
hdmi_set_cts_n(struct dw_hdmi * hdmi,unsigned int cts,unsigned int n)1758 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
1759 unsigned int n)
1760 {
1761 /* Must be set/cleared first */
1762 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
1763
1764 /* nshift factor = 0 */
1765 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
1766
1767 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
1768 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
1769 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
1770 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
1771
1772 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
1773 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
1774 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
1775 }
1776
hdmi_match_tmds_n_table(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned long freq)1777 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
1778 unsigned long pixel_clk,
1779 unsigned long freq)
1780 {
1781 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
1782 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
1783 int i;
1784
1785 if (plat_data->tmds_n_table) {
1786 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
1787 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
1788 tmds_n = &plat_data->tmds_n_table[i];
1789 break;
1790 }
1791 }
1792 }
1793
1794 if (!tmds_n) {
1795 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
1796 if (pixel_clk == common_tmds_n_table[i].tmds) {
1797 tmds_n = &common_tmds_n_table[i];
1798 break;
1799 }
1800 }
1801 }
1802
1803 if (!tmds_n)
1804 return -ENOENT;
1805
1806 switch (freq) {
1807 case 32000:
1808 return tmds_n->n_32k;
1809 case 44100:
1810 case 88200:
1811 case 176400:
1812 return (freq / 44100) * tmds_n->n_44k1;
1813 case 48000:
1814 case 96000:
1815 case 192000:
1816 return (freq / 48000) * tmds_n->n_48k;
1817 default:
1818 return -ENOENT;
1819 }
1820 }
1821
hdmi_audio_math_diff(unsigned int freq,unsigned int n,unsigned int pixel_clk)1822 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
1823 unsigned int pixel_clk)
1824 {
1825 u64 final, diff;
1826 u64 cts;
1827
1828 final = (u64)pixel_clk * n;
1829
1830 cts = final;
1831 do_div(cts, 128 * freq);
1832
1833 diff = final - (u64)cts * (128 * freq);
1834
1835 return diff;
1836 }
1837
hdmi_compute_n(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned long freq)1838 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
1839 unsigned long pixel_clk,
1840 unsigned long freq)
1841 {
1842 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
1843 unsigned int max_n = (128 * freq) / 300;
1844 unsigned int ideal_n = (128 * freq) / 1000;
1845 unsigned int best_n_distance = ideal_n;
1846 unsigned int best_n = 0;
1847 u64 best_diff = U64_MAX;
1848 int n;
1849
1850 /* If the ideal N could satisfy the audio math, then just take it */
1851 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
1852 return ideal_n;
1853
1854 for (n = min_n; n <= max_n; n++) {
1855 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
1856
1857 if (diff < best_diff || (diff == best_diff &&
1858 abs(n - ideal_n) < best_n_distance)) {
1859 best_n = n;
1860 best_diff = diff;
1861 best_n_distance = abs(best_n - ideal_n);
1862 }
1863
1864 /*
1865 * The best N already satisfy the audio math, and also be
1866 * the closest value to ideal N, so just cut the loop.
1867 */
1868 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
1869 break;
1870 }
1871
1872 return best_n;
1873 }
1874
hdmi_find_n(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned long sample_rate)1875 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
1876 unsigned long sample_rate)
1877 {
1878 int n;
1879
1880 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
1881 if (n > 0)
1882 return n;
1883
1884 printf("Rate %lu missing; compute N dynamically\n",
1885 pixel_clk);
1886
1887 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
1888 }
1889
1890 static
hdmi_set_clk_regenerator(struct dw_hdmi * hdmi,unsigned long pixel_clk,unsigned int sample_rate)1891 void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, unsigned long pixel_clk,
1892 unsigned int sample_rate)
1893 {
1894 unsigned long ftdms = pixel_clk;
1895 unsigned int n, cts;
1896 u64 tmp;
1897
1898 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
1899
1900 /*
1901 * Compute the CTS value from the N value. Note that CTS and N
1902 * can be up to 20 bits in total, so we need 64-bit math. Also
1903 * note that our TDMS clock is not fully accurate; it is accurate
1904 * to kHz. This can introduce an unnecessary remainder in the
1905 * calculation below, so we don't try to warn about that.
1906 */
1907 tmp = (u64)ftdms * n;
1908 do_div(tmp, 128 * sample_rate);
1909 cts = tmp;
1910
1911 printf("%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", __func__,
1912 sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, n, cts);
1913
1914 hdmi->audio_n = n;
1915 hdmi->audio_cts = cts;
1916 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
1917 }
1918
hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi * hdmi)1919 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
1920 {
1921 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
1922 hdmi->sample_rate);
1923 }
1924
hdmi_enable_audio_clk(struct dw_hdmi * hdmi)1925 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1926 {
1927 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1928 }
1929
dw_hdmi_set_sample_rate(struct dw_hdmi * hdmi,unsigned int rate)1930 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
1931 {
1932 hdmi->sample_rate = rate;
1933 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
1934 hdmi->sample_rate);
1935 }
1936
1937 #ifndef CONFIG_SPL_BUILD
dw_hdmi_hdcp_load_key(struct dw_hdmi * hdmi)1938 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi)
1939 {
1940 int i, j, ret, val;
1941 struct hdcp_keys *hdcp_keys;
1942
1943 val = sizeof(*hdcp_keys);
1944 hdcp_keys = malloc(val);
1945 if (!hdcp_keys)
1946 return -ENOMEM;
1947
1948 memset(hdcp_keys, 0, val);
1949
1950 ret = vendor_storage_read(HDMI_HDCP1X_ID, hdcp_keys, val);
1951 if (ret < val) {
1952 printf("HDCP: read size %d\n", ret);
1953 free(hdcp_keys);
1954 return -EINVAL;
1955 }
1956
1957 if (hdcp_keys->KSV[0] == 0x00 &&
1958 hdcp_keys->KSV[1] == 0x00 &&
1959 hdcp_keys->KSV[2] == 0x00 &&
1960 hdcp_keys->KSV[3] == 0x00 &&
1961 hdcp_keys->KSV[4] == 0x00) {
1962 printf("HDCP: Invalid hdcp key\n");
1963 free(hdcp_keys);
1964 return -EINVAL;
1965 }
1966
1967 /* Disable decryption logic */
1968 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_RMCTL);
1969 /* Poll untile DPK write is allowed */
1970 do {
1971 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS);
1972 } while ((val & DPK_WR_OK_STS) == 0);
1973
1974 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK6);
1975 hdmi_writeb(hdmi, 0, HDMI_HDCPREG_DPK5);
1976
1977 /* The useful data in ksv should be 5 byte */
1978 for (i = 4; i >= 0; i--)
1979 hdmi_writeb(hdmi, hdcp_keys->KSV[i], HDMI_HDCPREG_DPK0 + i);
1980 /* Poll untile DPK write is allowed */
1981 do {
1982 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS);
1983 } while ((val & DPK_WR_OK_STS) == 0);
1984
1985 /* Enable decryption logic */
1986 hdmi_writeb(hdmi, 1, HDMI_HDCPREG_RMCTL);
1987 hdmi_writeb(hdmi, hdcp_keys->seeds[0], HDMI_HDCPREG_SEED1);
1988 hdmi_writeb(hdmi, hdcp_keys->seeds[1], HDMI_HDCPREG_SEED0);
1989
1990 /* Write encrypt device private key */
1991 for (i = 0; i < DW_HDMI_HDCP_DPK_LEN - 6; i += 7) {
1992 for (j = 6; j >= 0; j--)
1993 hdmi_writeb(hdmi, hdcp_keys->devicekey[i + j],
1994 HDMI_HDCPREG_DPK0 + j);
1995 do {
1996 val = hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS);
1997 } while ((val & DPK_WR_OK_STS) == 0);
1998 }
1999
2000 free(hdcp_keys);
2001 return 0;
2002 }
2003 #endif
2004
hdmi_tx_hdcp_config(struct dw_hdmi * hdmi,const struct drm_display_mode * mode)2005 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi,
2006 const struct drm_display_mode *mode)
2007 {
2008 u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi;
2009
2010 if (!hdmi->hdcp1x_enable)
2011 return;
2012
2013 /* Configure the video polarity */
2014 vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ?
2015 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH :
2016 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW;
2017 hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ?
2018 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH :
2019 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW;
2020 data_pol = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
2021 hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol,
2022 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK |
2023 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK |
2024 HDMI_A_VIDPOLCFG_DATAENPOL_MASK,
2025 HDMI_A_VIDPOLCFG);
2026
2027 /* Config the display mode */
2028 hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI :
2029 HDMI_A_HDCPCFG0_HDMIDVI_DVI;
2030 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK,
2031 HDMI_A_HDCPCFG0);
2032
2033 #ifndef CONFIG_SPL_BUILD
2034 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f))
2035 dw_hdmi_hdcp_load_key(hdmi);
2036 #endif
2037
2038 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE,
2039 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK,
2040 HDMI_FC_INVIDCONF);
2041
2042 if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_A_HDCP22_MASK) {
2043 hdmi_modb(hdmi, HDMI_HDCP2_OVR_ENABLE |
2044 HDMI_HDCP2_FORCE_DISABLE,
2045 HDMI_HDCP2_OVR_EN_MASK |
2046 HDMI_HDCP2_FORCE_MASK,
2047 HDMI_HDCP2REG_CTRL);
2048 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MASK);
2049 hdmi_writeb(hdmi, 0xff, HDMI_HDCP2REG_MUTE);
2050 }
2051
2052 hdmi_writeb(hdmi, 0x40, HDMI_A_OESSWCFG);
2053 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE |
2054 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE |
2055 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE,
2056 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK |
2057 HDMI_A_HDCPCFG0_EN11FEATURE_MASK |
2058 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK, HDMI_A_HDCPCFG0);
2059
2060 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE |
2061 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE,
2062 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK |
2063 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK, HDMI_A_HDCPCFG1);
2064
2065 /* Reset HDCP Engine */
2066 if (hdmi_readb(hdmi, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_HDCPCLK_MASK) {
2067 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_SWRESET_ASSERT,
2068 HDMI_A_HDCPCFG1_SWRESET_MASK, HDMI_A_HDCPCFG1);
2069 }
2070
2071 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK);
2072 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_ENABLE,
2073 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
2074
2075 hdmi_modb(hdmi, HDMI_MC_CLKDIS_HDCPCLK_ENABLE,
2076 HDMI_MC_CLKDIS_HDCPCLK_MASK, HDMI_MC_CLKDIS);
2077
2078 printf("%s success\n", __func__);
2079 }
2080
dw_hdmi_setup(struct dw_hdmi * hdmi,struct rockchip_connector * conn,struct drm_display_mode * mode,struct display_state * state)2081 static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2082 struct rockchip_connector *conn,
2083 struct drm_display_mode *mode,
2084 struct display_state *state)
2085 {
2086 int ret;
2087 void *data = hdmi->plat_data->phy_data;
2088
2089 hdmi_disable_overflow_interrupts(hdmi);
2090 if (!hdmi->vic)
2091 printf("Non-CEA mode used in HDMI\n");
2092 else
2093 printf("CEA mode used vic=%d\n", hdmi->vic);
2094
2095 if (hdmi->plat_data->get_enc_out_encoding)
2096 hdmi->hdmi_data.enc_out_encoding =
2097 hdmi->plat_data->get_enc_out_encoding(data);
2098 else if (hdmi->vic == 6 || hdmi->vic == 7 ||
2099 hdmi->vic == 21 || hdmi->vic == 22 ||
2100 hdmi->vic == 2 || hdmi->vic == 3 ||
2101 hdmi->vic == 17 || hdmi->vic == 18)
2102 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2103 else
2104 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2105
2106 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2107 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
2108 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
2109 } else {
2110 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2111 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2112 }
2113
2114 /* TOFIX: Get input encoding from plat data or fallback to none */
2115 if (hdmi->plat_data->get_enc_in_encoding)
2116 hdmi->hdmi_data.enc_in_encoding =
2117 hdmi->plat_data->get_enc_in_encoding(data);
2118 else if (hdmi->plat_data->input_bus_encoding)
2119 hdmi->hdmi_data.enc_in_encoding =
2120 hdmi->plat_data->input_bus_encoding;
2121 else
2122 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2123
2124 if (hdmi->plat_data->get_quant_range)
2125 hdmi->hdmi_data.quant_range =
2126 hdmi->plat_data->get_quant_range(data);
2127 else
2128 hdmi->hdmi_data.quant_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
2129
2130 /*
2131 * According to the dw-hdmi specification 6.4.2
2132 * vp_pr_cd[3:0]:
2133 * 0000b: No pixel repetition (pixel sent only once)
2134 * 0001b: Pixel sent two times (pixel repeated once)
2135 */
2136 hdmi->hdmi_data.pix_repet_factor =
2137 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
2138 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2139
2140 /* HDMI Initialization Step B.1 */
2141 hdmi_av_composer(hdmi, mode);
2142
2143 /* HDMI Initialization Step B.2 */
2144 ret = hdmi->phy.ops->init(conn, hdmi, state);
2145 if (ret)
2146 return ret;
2147 hdmi->phy.enabled = true;
2148
2149 /* HDMI Initializateion Step B.3 */
2150 dw_hdmi_enable_video_path(hdmi);
2151
2152 /* HDMI Initialization Step E - Configure audio */
2153 if (hdmi->sink_has_audio) {
2154 printf("sink has audio support\n");
2155 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2156 hdmi_enable_audio_clk(hdmi);
2157 }
2158
2159 /* not for DVI mode */
2160 if (hdmi->sink_is_hdmi) {
2161 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2162 hdmi_config_AVI(hdmi, mode);
2163 hdmi_config_vendor_specific_infoframe(hdmi, mode);
2164 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_HDMI,
2165 HDMI_A_HDCPCFG0_HDMIDVI_MASK,
2166 HDMI_A_HDCPCFG0);
2167 } else {
2168 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_HDMIDVI_DVI,
2169 HDMI_A_HDCPCFG0_HDMIDVI_MASK,
2170 HDMI_A_HDCPCFG0);
2171 printf("%s DVI mode\n", __func__);
2172 }
2173
2174 hdmi_video_packetize(hdmi);
2175 hdmi_video_csc(hdmi);
2176 hdmi_video_sample(hdmi);
2177 hdmi_tx_hdcp_config(hdmi, mode);
2178 dw_hdmi_clear_overflow(hdmi);
2179
2180 return 0;
2181 }
2182
dw_hdmi_detect_hotplug(struct dw_hdmi * hdmi,struct display_state * state)2183 int dw_hdmi_detect_hotplug(struct dw_hdmi *hdmi,
2184 struct display_state *state)
2185 {
2186 return hdmi->phy.ops->read_hpd(hdmi, state);
2187 }
2188
dw_hdmi_set_reg_wr(struct dw_hdmi * hdmi)2189 static int dw_hdmi_set_reg_wr(struct dw_hdmi *hdmi)
2190 {
2191 switch (hdmi->io_width) {
2192 case 4:
2193 hdmi->write = dw_hdmi_writel;
2194 hdmi->read = dw_hdmi_readl;
2195 break;
2196 case 1:
2197 hdmi->write = dw_hdmi_writeb;
2198 hdmi->read = dw_hdmi_readb;
2199 break;
2200 default:
2201 printf("reg-io-width must be 1 or 4\n");
2202 return -EINVAL;
2203 }
2204
2205 return 0;
2206 }
2207
initialize_hdmi_mutes(struct dw_hdmi * hdmi)2208 static void initialize_hdmi_mutes(struct dw_hdmi *hdmi)
2209 {
2210 /*mute unnecessary interrupt, only enable hpd */
2211 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2212 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2213 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2214 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2215 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2216 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2217 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2218 hdmi_writeb(hdmi, 0xfe, HDMI_IH_MUTE_PHY_STAT0);
2219 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2220 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2221 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2222 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2223 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2224 hdmi_writeb(hdmi, 0xf1, HDMI_PHY_MASK0);
2225
2226 /*Force output black*/
2227 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS2);
2228 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS1);
2229 dw_hdmi_writel(hdmi, 0x00, HDMI_FC_DBGTMDS0);
2230 }
2231
dw_hdmi_dev_init(struct dw_hdmi * hdmi)2232 static void dw_hdmi_dev_init(struct dw_hdmi *hdmi)
2233 {
2234 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2235 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2236
2237 initialize_hdmi_mutes(hdmi);
2238 }
2239
dw_hdmi_i2c_set_divs(struct dw_hdmi * hdmi)2240 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)
2241 {
2242 unsigned long low_ns, high_ns;
2243 unsigned long div_low, div_high;
2244
2245 /* Standard-mode */
2246 if (hdmi->i2c->scl_high_ns < 4000)
2247 high_ns = 4708;
2248 else
2249 high_ns = hdmi->i2c->scl_high_ns;
2250
2251 if (hdmi->i2c->scl_low_ns < 4700)
2252 low_ns = 4916;
2253 else
2254 low_ns = hdmi->i2c->scl_low_ns;
2255
2256 div_low = (24000 * low_ns) / 1000000;
2257 if ((24000 * low_ns) % 1000000)
2258 div_low++;
2259
2260 div_high = (24000 * high_ns) / 1000000;
2261 if ((24000 * high_ns) % 1000000)
2262 div_high++;
2263
2264 /* Maximum divider supported by hw is 0xffff */
2265 if (div_low > 0xffff)
2266 div_low = 0xffff;
2267
2268 if (div_high > 0xffff)
2269 div_high = 0xffff;
2270
2271 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
2272 hdmi_writeb(hdmi, (div_high >> 8) & 0xff,
2273 HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
2274 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
2275 hdmi_writeb(hdmi, (div_low >> 8) & 0xff,
2276 HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
2277 }
2278
dw_hdmi_i2c_init(struct dw_hdmi * hdmi)2279 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
2280 {
2281 /* Software reset */
2282 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
2283
2284 /* Set Standard Mode speed */
2285 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
2286 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
2287
2288 /* Set done, not acknowledged and arbitration interrupt polarities */
2289 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
2290 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
2291 HDMI_I2CM_CTLINT);
2292
2293 /* Clear DONE and ERROR interrupts */
2294 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
2295 HDMI_IH_I2CM_STAT0);
2296
2297 /* Mute DONE and ERROR interrupts */
2298 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
2299 HDMI_IH_MUTE_I2CM_STAT0);
2300
2301 /* set SDA high level holding time */
2302 hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
2303
2304 dw_hdmi_i2c_set_divs(hdmi);
2305 }
2306
dw_hdmi_audio_enable(struct dw_hdmi * hdmi)2307 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
2308 {
2309 hdmi->audio_enable = true;
2310 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
2311 }
2312
dw_hdmi_audio_disable(struct dw_hdmi * hdmi)2313 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
2314 {
2315 hdmi->audio_enable = false;
2316 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
2317 }
2318
rockchip_dw_hdmi_init(struct rockchip_connector * conn,struct display_state * state)2319 int rockchip_dw_hdmi_init(struct rockchip_connector *conn, struct display_state *state)
2320 {
2321 struct connector_state *conn_state = &state->conn_state;
2322 const struct dw_hdmi_plat_data *pdata =
2323 #ifdef CONFIG_SPL_BUILD
2324 (const struct dw_hdmi_plat_data *)conn->data;
2325 #else
2326 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev);
2327 ofnode hdmi_node = conn->dev->node;
2328 struct device_node *ddc_node;
2329 int ret;
2330 #endif
2331 struct crtc_state *crtc_state = &state->crtc_state;
2332 struct dw_hdmi *hdmi;
2333 struct drm_display_mode *mode_buf;
2334 u32 val;
2335
2336 hdmi = malloc(sizeof(struct dw_hdmi));
2337 if (!hdmi)
2338 return -ENOMEM;
2339
2340 memset(hdmi, 0, sizeof(struct dw_hdmi));
2341 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode));
2342 if (!mode_buf)
2343 return -ENOMEM;
2344
2345 #ifdef CONFIG_SPL_BUILD
2346 hdmi->id = 0;
2347 hdmi->regs = (void *)RK3528_HDMI_BASE;
2348 hdmi->io_width = 4;
2349 hdmi->scramble_low_rates = false;
2350 hdmi->hdcp1x_enable = false;
2351 hdmi->output_bus_format_rgb = false;
2352 conn_state->type = DRM_MODE_CONNECTOR_HDMIA;
2353 #else
2354 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi");
2355 if (hdmi->id < 0)
2356 hdmi->id = 0;
2357 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
2358 #endif
2359
2360 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode));
2361
2362 hdmi->dev_type = pdata->dev_type;
2363 hdmi->plat_data = pdata;
2364
2365 #ifndef CONFIG_SPL_BUILD
2366 hdmi->regs = dev_read_addr_ptr(conn->dev);
2367 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1);
2368
2369 if (ofnode_read_bool(hdmi_node, "scramble-low-rates"))
2370 hdmi->scramble_low_rates = true;
2371
2372 if (ofnode_read_bool(hdmi_node, "hdcp1x-enable"))
2373 hdmi->hdcp1x_enable = true;
2374 else
2375 hdmi->hdcp1x_enable = false;
2376
2377 if (ofnode_read_bool(hdmi_node, "force_output_bus_format_RGB") ||
2378 ofnode_read_bool(hdmi_node, "unsupported-yuv-input"))
2379 hdmi->output_bus_format_rgb = true;
2380 else
2381 hdmi->output_bus_format_rgb = false;
2382
2383 ret = dev_read_size(conn->dev, "rockchip,phy-table");
2384 if (ret > 0 && hdmi->plat_data->phy_config) {
2385 u32 phy_config[ret / 4];
2386 int i;
2387
2388 dev_read_u32_array(conn->dev, "rockchip,phy-table", phy_config, ret / 4);
2389
2390 for (i = 0; i < ret / 16; i++) {
2391 if (phy_config[i * 4] != 0)
2392 hdmi->plat_data->phy_config[i].mpixelclock = (u64)phy_config[i * 4];
2393 else
2394 hdmi->plat_data->phy_config[i].mpixelclock = ~0UL;
2395 hdmi->plat_data->phy_config[i].sym_ctr = (u16)phy_config[i * 4 + 1];
2396 hdmi->plat_data->phy_config[i].term = (u16)phy_config[i * 4 + 2];
2397 hdmi->plat_data->phy_config[i].vlev_ctr = (u16)phy_config[i * 4 + 3];
2398 }
2399 }
2400
2401 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0);
2402 if (ddc_node) {
2403 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node),
2404 &hdmi->adap.i2c_bus);
2405 if (hdmi->adap.i2c_bus)
2406 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus);
2407 }
2408 #endif
2409
2410 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
2411 if (hdmi->grf <= 0) {
2412 printf("%s: Get syscon grf failed (ret=%p)\n",
2413 __func__, hdmi->grf);
2414 return -ENXIO;
2415 }
2416
2417 #ifdef CONFIG_SPL_BUILD
2418 hdmi->gpio_base = (void *)RK3528_GPIO_BASE;
2419 #else
2420 ret = gpio_request_by_name(conn->dev, "hpd-gpios", 0,
2421 &hdmi->hpd_gpiod, GPIOD_IS_IN);
2422 if (ret && ret != -ENOENT) {
2423 printf("%s: Cannot get HPD GPIO: %d\n", __func__, ret);
2424 return ret;
2425 }
2426 hdmi->gpio_base = (void *)dev_read_addr_index(conn->dev, 1);
2427 #endif
2428 if (!hdmi->gpio_base)
2429 return -ENODEV;
2430
2431 dw_hdmi_set_reg_wr(hdmi);
2432
2433 if (pdata->grf_vop_sel_reg) {
2434 if (crtc_state->crtc_id)
2435 val = ((1 << pdata->vop_sel_bit) |
2436 (1 << (16 + pdata->vop_sel_bit)));
2437 else
2438 val = ((0 << pdata->vop_sel_bit) |
2439 (1 << (16 + pdata->vop_sel_bit)));
2440 writel(val, hdmi->grf + pdata->grf_vop_sel_reg);
2441 }
2442
2443 hdmi->i2c = malloc(sizeof(struct dw_hdmi_i2c));
2444 if (!hdmi->i2c)
2445 return -ENOMEM;
2446 hdmi->adap.ddc_xfer = dw_hdmi_i2c_xfer;
2447
2448 /*
2449 * Read high and low time from device tree. If not available use
2450 * the default timing scl clock rate is about 99.6KHz.
2451 */
2452 #ifdef CONFIG_SPL_BUILD
2453 hdmi->i2c->scl_high_ns = 9625;
2454 hdmi->i2c->scl_low_ns = 10000;
2455 #else
2456 hdmi->i2c->scl_high_ns =
2457 ofnode_read_s32_default(hdmi_node,
2458 "ddc-i2c-scl-high-time-ns", 4708);
2459 hdmi->i2c->scl_low_ns =
2460 ofnode_read_s32_default(hdmi_node,
2461 "ddc-i2c-scl-low-time-ns", 4916);
2462 #endif
2463
2464 dw_hdmi_i2c_init(hdmi);
2465 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0;
2466 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
2467
2468 hdmi->edid_data.mode_buf = mode_buf;
2469 hdmi->sample_rate = 48000;
2470
2471 conn->data = hdmi;
2472 dw_hdmi_set_iomux(hdmi->grf, hdmi->gpio_base,
2473 &hdmi->hpd_gpiod, hdmi->dev_type);
2474 dw_hdmi_detect_phy(hdmi);
2475 dw_hdmi_dev_init(hdmi);
2476
2477 return 0;
2478 }
2479
rockchip_dw_hdmi_deinit(struct rockchip_connector * conn,struct display_state * state)2480 void rockchip_dw_hdmi_deinit(struct rockchip_connector *conn, struct display_state *state)
2481 {
2482 struct dw_hdmi *hdmi = conn->data;
2483
2484 if (hdmi->i2c)
2485 free(hdmi->i2c);
2486 if (hdmi->edid_data.mode_buf)
2487 free(hdmi->edid_data.mode_buf);
2488 if (hdmi)
2489 free(hdmi);
2490 }
2491
rockchip_dw_hdmi_prepare(struct rockchip_connector * conn,struct display_state * state)2492 int rockchip_dw_hdmi_prepare(struct rockchip_connector *conn, struct display_state *state)
2493 {
2494 return 0;
2495 }
2496
rockchip_dw_hdmi_enable(struct rockchip_connector * conn,struct display_state * state)2497 int rockchip_dw_hdmi_enable(struct rockchip_connector *conn, struct display_state *state)
2498 {
2499 struct connector_state *conn_state = &state->conn_state;
2500 struct drm_display_mode *mode = &conn_state->mode;
2501 struct dw_hdmi *hdmi = conn->data;
2502
2503 if (!hdmi)
2504 return -EFAULT;
2505
2506 /* Store the display mode for plugin/DKMS poweron events */
2507 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2508
2509 dw_hdmi_setup(hdmi, conn, mode, state);
2510
2511 return 0;
2512 }
2513
rockchip_dw_hdmi_disable(struct rockchip_connector * conn,struct display_state * state)2514 int rockchip_dw_hdmi_disable(struct rockchip_connector *conn, struct display_state *state)
2515 {
2516 struct dw_hdmi *hdmi = conn->data;
2517
2518 dw_hdmi_disable(conn, hdmi, state);
2519 return 0;
2520 }
2521
rockchip_dw_hdmi_get_timing(struct rockchip_connector * conn,struct display_state * state)2522 int rockchip_dw_hdmi_get_timing(struct rockchip_connector *conn, struct display_state *state)
2523 {
2524 int ret, i, vic;
2525 struct connector_state *conn_state = &state->conn_state;
2526 struct drm_display_mode *mode = &conn_state->mode;
2527 struct dw_hdmi *hdmi = conn->data;
2528 struct edid *edid = (struct edid *)conn_state->edid;
2529 unsigned int bus_format;
2530 unsigned long enc_out_encoding;
2531 struct overscan *overscan = &conn_state->overscan;
2532 const u8 def_modes_vic[6] = {4, 16, 2, 17, 31, 19};
2533
2534 if (!hdmi)
2535 return -EFAULT;
2536
2537 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
2538
2539 if (!ret) {
2540 hdmi->sink_is_hdmi =
2541 drm_detect_hdmi_monitor(edid);
2542 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2543 ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
2544 }
2545 if (ret < 0) {
2546 hdmi->sink_is_hdmi = true;
2547 hdmi->sink_has_audio = true;
2548 do_cea_modes(&hdmi->edid_data, def_modes_vic,
2549 sizeof(def_modes_vic));
2550 hdmi->edid_data.mode_buf[0].type |= DRM_MODE_TYPE_PREFERRED;
2551 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0];
2552 printf("failed to get edid\n");
2553 }
2554 #ifdef CONFIG_SPL_BUILD
2555 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
2556 #endif
2557 drm_rk_filter_whitelist(&hdmi->edid_data);
2558 if (hdmi->phy.ops->mode_valid)
2559 hdmi->phy.ops->mode_valid(conn, hdmi, state);
2560 drm_mode_max_resolution_filter(&hdmi->edid_data,
2561 &state->crtc_state.max_output);
2562 if (!drm_mode_prune_invalid(&hdmi->edid_data)) {
2563 printf("can't find valid hdmi mode\n");
2564 return -EINVAL;
2565 }
2566
2567 for (i = 0; i < hdmi->edid_data.modes; i++) {
2568 hdmi->edid_data.mode_buf[i].vrefresh =
2569 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]);
2570
2571 vic = drm_match_cea_mode(&hdmi->edid_data.mode_buf[i]);
2572 if (hdmi->edid_data.mode_buf[i].picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) {
2573 if (vic >= 93 && vic <= 95)
2574 hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
2575 HDMI_PICTURE_ASPECT_16_9;
2576 else if (vic == 98)
2577 hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
2578 HDMI_PICTURE_ASPECT_256_135;
2579 }
2580 }
2581
2582 drm_mode_sort(&hdmi->edid_data);
2583 drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format,
2584 overscan, hdmi->dev_type, hdmi->output_bus_format_rgb);
2585
2586 *mode = *hdmi->edid_data.preferred_mode;
2587 hdmi->vic = drm_match_cea_mode(mode);
2588
2589 if (state->force_output)
2590 bus_format = state->force_bus_format;
2591 conn_state->bus_format = bus_format;
2592 hdmi->hdmi_data.enc_in_bus_format = bus_format;
2593 hdmi->hdmi_data.enc_out_bus_format = bus_format;
2594
2595 switch (bus_format) {
2596 case MEDIA_BUS_FMT_UYVY10_1X20:
2597 conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30;
2598 hdmi->hdmi_data.enc_in_bus_format =
2599 MEDIA_BUS_FMT_YUV10_1X30;
2600 break;
2601 case MEDIA_BUS_FMT_UYVY8_1X16:
2602 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
2603 hdmi->hdmi_data.enc_in_bus_format =
2604 MEDIA_BUS_FMT_YUV8_1X24;
2605 break;
2606 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2607 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2608 conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV420;
2609 break;
2610 }
2611
2612 if (hdmi->vic == 6 || hdmi->vic == 7 || hdmi->vic == 21 ||
2613 hdmi->vic == 22 || hdmi->vic == 2 || hdmi->vic == 3 ||
2614 hdmi->vic == 17 || hdmi->vic == 18)
2615 enc_out_encoding = V4L2_YCBCR_ENC_601;
2616 else
2617 enc_out_encoding = V4L2_YCBCR_ENC_709;
2618
2619 if (enc_out_encoding == V4L2_YCBCR_ENC_BT2020)
2620 conn_state->color_space = V4L2_COLORSPACE_BT2020;
2621 else if (bus_format == MEDIA_BUS_FMT_RGB888_1X24 ||
2622 bus_format == MEDIA_BUS_FMT_RGB101010_1X30)
2623 conn_state->color_space = V4L2_COLORSPACE_DEFAULT;
2624 else if (enc_out_encoding == V4L2_YCBCR_ENC_709)
2625 conn_state->color_space = V4L2_COLORSPACE_REC709;
2626 else
2627 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M;
2628
2629 return 0;
2630 }
2631
rockchip_dw_hdmi_detect(struct rockchip_connector * conn,struct display_state * state)2632 int rockchip_dw_hdmi_detect(struct rockchip_connector *conn, struct display_state *state)
2633 {
2634 int ret;
2635 struct dw_hdmi *hdmi = conn->data;
2636
2637 if (!hdmi)
2638 return -EFAULT;
2639
2640 ret = dw_hdmi_detect_hotplug(hdmi, state);
2641
2642 return ret;
2643 }
2644
rockchip_dw_hdmi_get_edid(struct rockchip_connector * conn,struct display_state * state)2645 int rockchip_dw_hdmi_get_edid(struct rockchip_connector *conn, struct display_state *state)
2646 {
2647 int ret;
2648 struct connector_state *conn_state = &state->conn_state;
2649 struct dw_hdmi *hdmi = conn->data;
2650
2651 ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
2652
2653 return ret;
2654 }
2655
inno_dw_hdmi_phy_init(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)2656 int inno_dw_hdmi_phy_init(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data)
2657 {
2658 struct display_state *state = (struct display_state *)data;
2659 struct connector_state *conn_state = &state->conn_state;
2660 u32 color_depth, bus_width;
2661
2662 color_depth =
2663 hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format);
2664
2665 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2666 bus_width = color_depth / 2;
2667 else if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
2668 bus_width = color_depth;
2669 else
2670 bus_width = 8;
2671 rockchip_phy_set_bus_width(conn->phy, bus_width);
2672 rockchip_phy_set_pll(conn->phy,
2673 conn_state->mode.crtc_clock * 1000);
2674 if (hdmi->edid_data.display_info.hdmi.scdc.supported)
2675 rockchip_dw_hdmi_scdc_set_tmds_rate(hdmi);
2676 rockchip_phy_power_on(conn->phy);
2677
2678 return 0;
2679 }
2680
inno_dw_hdmi_phy_disable(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)2681 void inno_dw_hdmi_phy_disable(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data)
2682 {
2683 }
2684
2685 enum drm_connector_status
inno_dw_hdmi_phy_read_hpd(struct dw_hdmi * hdmi,void * data)2686 inno_dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, void *data)
2687 {
2688 enum drm_connector_status status;
2689 struct display_state *state = (struct display_state *)data;
2690
2691 status = dw_hdmi_phy_read_hpd(hdmi, state);
2692
2693 if (hdmi->dev_type == RK3328_HDMI) {
2694 if (status == connector_status_connected)
2695 inno_dw_hdmi_set_domain(hdmi->grf, 1);
2696 else
2697 inno_dw_hdmi_set_domain(hdmi->grf, 0);
2698 }
2699
2700 return status;
2701 }
2702
inno_dw_hdmi_mode_valid(struct rockchip_connector * conn,struct dw_hdmi * hdmi,void * data)2703 void inno_dw_hdmi_mode_valid(struct rockchip_connector *conn, struct dw_hdmi *hdmi, void *data)
2704 {
2705 struct hdmi_edid_data *edid_data = &hdmi->edid_data;
2706 unsigned long rate;
2707 int i, ret;
2708 struct drm_display_mode *mode_buf = edid_data->mode_buf;
2709
2710 for (i = 0; i < edid_data->modes; i++) {
2711 if (edid_data->mode_buf[i].invalid)
2712 continue;
2713 if (edid_data->mode_buf[i].flags & DRM_MODE_FLAG_DBLCLK)
2714 rate = mode_buf[i].clock * 1000 * 2;
2715 else
2716 rate = mode_buf[i].clock * 1000;
2717
2718 /* Check whether mode is out of phy cfg range. */
2719 ret = rockchip_phy_round_rate(conn->phy, rate);
2720
2721 if (ret < 0)
2722 edid_data->mode_buf[i].invalid = true;
2723 }
2724 }
2725