1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Porting to u-boot: 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2011 5*4882a593Smuzhiyun * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2008-2009 MontaVista Software Inc. 8*4882a593Smuzhiyun * Copyright (C) 2008-2009 Texas Instruments Inc 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Based on the LCD driver for TI Avalanche processors written by 11*4882a593Smuzhiyun * Ajay Singh and Shalom Hai. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef DA8XX_FB_H 17*4882a593Smuzhiyun #define DA8XX_FB_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum panel_type { 20*4882a593Smuzhiyun QVGA = 0, 21*4882a593Smuzhiyun WVGA 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun enum panel_shade { 25*4882a593Smuzhiyun MONOCHROME = 0, 26*4882a593Smuzhiyun COLOR_ACTIVE, 27*4882a593Smuzhiyun COLOR_PASSIVE, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum raster_load_mode { 31*4882a593Smuzhiyun LOAD_DATA = 1, 32*4882a593Smuzhiyun LOAD_PALETTE, 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct display_panel { 36*4882a593Smuzhiyun enum panel_type panel_type; /* QVGA */ 37*4882a593Smuzhiyun int max_bpp; 38*4882a593Smuzhiyun int min_bpp; 39*4882a593Smuzhiyun enum panel_shade panel_shade; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct da8xx_panel { 43*4882a593Smuzhiyun const char name[25]; /* Full name <vendor>_<model> */ 44*4882a593Smuzhiyun unsigned short width; 45*4882a593Smuzhiyun unsigned short height; 46*4882a593Smuzhiyun int hfp; /* Horizontal front porch */ 47*4882a593Smuzhiyun int hbp; /* Horizontal back porch */ 48*4882a593Smuzhiyun int hsw; /* Horizontal Sync Pulse Width */ 49*4882a593Smuzhiyun int vfp; /* Vertical front porch */ 50*4882a593Smuzhiyun int vbp; /* Vertical back porch */ 51*4882a593Smuzhiyun int vsw; /* Vertical Sync Pulse Width */ 52*4882a593Smuzhiyun unsigned int pxl_clk; /* Pixel clock */ 53*4882a593Smuzhiyun unsigned char invert_pxl_clk; /* Invert Pixel clock */ 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun struct da8xx_lcdc_platform_data { 57*4882a593Smuzhiyun const char manu_name[10]; 58*4882a593Smuzhiyun void *controller_data; 59*4882a593Smuzhiyun const char type[25]; 60*4882a593Smuzhiyun void (*panel_power_ctrl)(int); 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct lcd_ctrl_config { 64*4882a593Smuzhiyun const struct display_panel *p_disp_panel; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* AC Bias Pin Frequency */ 67*4882a593Smuzhiyun int ac_bias; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* AC Bias Pin Transitions per Interrupt */ 70*4882a593Smuzhiyun int ac_bias_intrpt; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* DMA burst size */ 73*4882a593Smuzhiyun int dma_burst_sz; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Bits per pixel */ 76*4882a593Smuzhiyun int bpp; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* FIFO DMA Request Delay */ 79*4882a593Smuzhiyun int fdd; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* TFT Alternative Signal Mapping (Only for active) */ 82*4882a593Smuzhiyun unsigned char tft_alt_mode; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ 85*4882a593Smuzhiyun unsigned char stn_565_mode; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ 88*4882a593Smuzhiyun unsigned char mono_8bit_mode; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Invert line clock */ 91*4882a593Smuzhiyun unsigned char invert_line_clock; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Invert frame clock */ 94*4882a593Smuzhiyun unsigned char invert_frm_clock; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ 97*4882a593Smuzhiyun unsigned char sync_edge; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* Horizontal and Vertical Sync: Control: 0=ignore */ 100*4882a593Smuzhiyun unsigned char sync_ctrl; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ 103*4882a593Smuzhiyun unsigned char raster_order; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun struct lcd_sync_arg { 107*4882a593Smuzhiyun int back_porch; 108*4882a593Smuzhiyun int front_porch; 109*4882a593Smuzhiyun int pulse_width; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun void da8xx_video_init(const struct da8xx_panel *panel, 113*4882a593Smuzhiyun const struct lcd_ctrl_config *lcd_cfg, 114*4882a593Smuzhiyun int bits_pixel); 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif /* ifndef DA8XX_FB_H */ 117