1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com> 3*4882a593Smuzhiyun * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* Registers at i2c address 0x38 */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define ANX9804_HDCP_CONTROL_0_REG 0x01 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_REG 0x80 13*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_PD_IO 0x80 14*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_PD_VID 0x40 15*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_PD_LINK 0x20 16*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_PD_TOTAL 0x10 17*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_MODE_SEL 0x08 18*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_DET_STA 0x04 19*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_FORCE_DET 0x02 20*4882a593Smuzhiyun #define ANX9804_SYS_CTRL1_DET_CTRL 0x01 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define ANX9804_SYS_CTRL2_REG 0x81 23*4882a593Smuzhiyun #define ANX9804_SYS_CTRL2_CHA_STA 0x04 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define ANX9804_SYS_CTRL3_REG 0x82 26*4882a593Smuzhiyun #define ANX9804_SYS_CTRL3_VALID_CTRL BIT(0) 27*4882a593Smuzhiyun #define ANX9804_SYS_CTRL3_F_VALID BIT(1) 28*4882a593Smuzhiyun #define ANX9804_SYS_CTRL3_HPD_CTRL BIT(4) 29*4882a593Smuzhiyun #define ANX9804_SYS_CTRL3_F_HPD BIT(5) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define ANX9804_LINK_BW_SET_REG 0xa0 32*4882a593Smuzhiyun #define ANX9804_LANE_COUNT_SET_REG 0xa1 33*4882a593Smuzhiyun #define ANX9804_TRAINING_PTN_SET_REG 0xa2 34*4882a593Smuzhiyun #define ANX9804_TRAINING_LANE0_SET_REG 0xa3 35*4882a593Smuzhiyun #define ANX9804_TRAINING_LANE1_SET_REG 0xa4 36*4882a593Smuzhiyun #define ANX9804_TRAINING_LANE2_SET_REG 0xa5 37*4882a593Smuzhiyun #define ANX9804_TRAINING_LANE3_SET_REG 0xa6 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define ANX9804_LINK_TRAINING_CTRL_REG 0xa8 40*4882a593Smuzhiyun #define ANX9804_LINK_TRAINING_CTRL_EN BIT(0) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define ANX9804_LINK_DEBUG_REG 0xb8 43*4882a593Smuzhiyun #define ANX9804_PLL_CTRL_REG 0xc7 44*4882a593Smuzhiyun #define ANX9804_ANALOG_POWER_DOWN_REG 0xc8 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define ANX9804_AUX_CH_STA 0xe0 47*4882a593Smuzhiyun #define ANX9804_AUX_BUSY BIT(4) 48*4882a593Smuzhiyun #define ANX9804_AUX_STATUS_MASK 0x0f 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define ANX9804_DP_AUX_RX_COMM 0xe3 51*4882a593Smuzhiyun #define ANX9804_AUX_RX_COMM_I2C_DEFER BIT(3) 52*4882a593Smuzhiyun #define ANX9804_AUX_RX_COMM_AUX_DEFER BIT(1) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define ANX9804_DP_AUX_CH_CTL_1 0xe5 55*4882a593Smuzhiyun #define ANX9804_AUX_LENGTH(x) (((x - 1) & 0x0f) << 4) 56*4882a593Smuzhiyun #define ANX9804_AUX_TX_COMM_MASK 0x0f 57*4882a593Smuzhiyun #define ANX9804_AUX_TX_COMM_DP_TRANSACTION BIT(3) 58*4882a593Smuzhiyun #define ANX9804_AUX_TX_COMM_MOT BIT(2) 59*4882a593Smuzhiyun #define ANX9804_AUX_TX_COMM_READ BIT(0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define ANX9804_DP_AUX_ADDR_7_0 0xe6 62*4882a593Smuzhiyun #define ANX9804_DP_AUX_ADDR_15_8 0xe7 63*4882a593Smuzhiyun #define ANX9804_DP_AUX_ADDR_19_16 0xe8 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define ANX9804_DP_AUX_CH_CTL_2 0xe9 66*4882a593Smuzhiyun #define ANX9804_ADDR_ONLY BIT(1) 67*4882a593Smuzhiyun #define ANX9804_AUX_EN BIT(0) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define ANX9804_BUF_DATA_0 0xf0 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Registers at i2c address 0x39 */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define ANX9804_DEV_IDH_REG 0x03 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define ANX9804_POWERD_CTRL_REG 0x05 76*4882a593Smuzhiyun #define ANX9804_POWERD_AUDIO BIT(4) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define ANX9804_RST_CTRL_REG 0x06 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define ANX9804_RST_CTRL2_REG 0x07 81*4882a593Smuzhiyun #define ANX9804_RST_CTRL2_AUX BIT(2) 82*4882a593Smuzhiyun #define ANX9804_RST_CTRL2_AC_MODE BIT(6) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define ANX9804_VID_CTRL1_REG 0x08 85*4882a593Smuzhiyun #define ANX9804_VID_CTRL1_VID_EN BIT(7) 86*4882a593Smuzhiyun #define ANX9804_VID_CTRL1_DDR_CTRL BIT(1) 87*4882a593Smuzhiyun #define ANX9804_VID_CTRL1_EDGE BIT(0) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define ANX9804_VID_CTRL2_REG 0x09 90*4882a593Smuzhiyun #define ANX9804_ANALOG_DEBUG_REG1 0xdc 91*4882a593Smuzhiyun #define ANX9804_ANALOG_DEBUG_REG3 0xde 92*4882a593Smuzhiyun #define ANX9804_PLL_FILTER_CTRL1 0xdf 93*4882a593Smuzhiyun #define ANX9804_PLL_FILTER_CTRL3 0xe1 94*4882a593Smuzhiyun #define ANX9804_PLL_FILTER_CTRL 0xe2 95*4882a593Smuzhiyun #define ANX9804_PLL_CTRL3 0xe6 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define ANX9804_DP_INT_STA 0xf7 98*4882a593Smuzhiyun #define ANX9804_RPLY_RECEIV BIT(1) 99*4882a593Smuzhiyun #define ANX9804_AUX_ERR BIT(0) 100