1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
3*4882a593Smuzhiyun * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * minimal framebuffer driver for TI's AM335x SoC to be compatible with
6*4882a593Smuzhiyun * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
9*4882a593Smuzhiyun * - sets up LCD controller as in 'am335x_lcdpanel' struct given
10*4882a593Smuzhiyun * - starts output DMA from gd->fb_base buffer
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun #include <common.h>
15*4882a593Smuzhiyun #include <asm/arch/hardware.h>
16*4882a593Smuzhiyun #include <lcd.h>
17*4882a593Smuzhiyun #include "am335x-fb.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #if !defined(LCD_CNTL_BASE)
20*4882a593Smuzhiyun #error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* LCD Control Register */
25*4882a593Smuzhiyun #define LCD_CLK_DIVISOR(x) ((x) << 8)
26*4882a593Smuzhiyun #define LCD_RASTER_MODE 0x01
27*4882a593Smuzhiyun /* LCD Clock Enable Register */
28*4882a593Smuzhiyun #define LCD_CORECLKEN (0x01 << 0)
29*4882a593Smuzhiyun #define LCD_LIDDCLKEN (0x01 << 1)
30*4882a593Smuzhiyun #define LCD_DMACLKEN (0x01 << 2)
31*4882a593Smuzhiyun /* LCD DMA Control Register */
32*4882a593Smuzhiyun #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
33*4882a593Smuzhiyun #define LCD_DMA_BURST_1 0x0
34*4882a593Smuzhiyun #define LCD_DMA_BURST_2 0x1
35*4882a593Smuzhiyun #define LCD_DMA_BURST_4 0x2
36*4882a593Smuzhiyun #define LCD_DMA_BURST_8 0x3
37*4882a593Smuzhiyun #define LCD_DMA_BURST_16 0x4
38*4882a593Smuzhiyun /* LCD Timing_0 Register */
39*4882a593Smuzhiyun #define LCD_HBPLSB(x) ((((x)-1) & 0xFF) << 24)
40*4882a593Smuzhiyun #define LCD_HFPLSB(x) ((((x)-1) & 0xFF) << 16)
41*4882a593Smuzhiyun #define LCD_HSWLSB(x) ((((x)-1) & 0x3F) << 10)
42*4882a593Smuzhiyun #define LCD_HORLSB(x) (((((x) >> 4)-1) & 0x3F) << 4)
43*4882a593Smuzhiyun #define LCD_HORMSB(x) (((((x) >> 4)-1) & 0x40) >> 4)
44*4882a593Smuzhiyun /* LCD Timing_1 Register */
45*4882a593Smuzhiyun #define LCD_VBP(x) ((x) << 24)
46*4882a593Smuzhiyun #define LCD_VFP(x) ((x) << 16)
47*4882a593Smuzhiyun #define LCD_VSW(x) (((x)-1) << 10)
48*4882a593Smuzhiyun #define LCD_VERLSB(x) (((x)-1) & 0x3FF)
49*4882a593Smuzhiyun /* LCD Timing_2 Register */
50*4882a593Smuzhiyun #define LCD_HSWMSB(x) ((((x)-1) & 0x3C0) << 21)
51*4882a593Smuzhiyun #define LCD_VERMSB(x) ((((x)-1) & 0x400) << 16)
52*4882a593Smuzhiyun #define LCD_HBPMSB(x) ((((x)-1) & 0x300) >> 4)
53*4882a593Smuzhiyun #define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8)
54*4882a593Smuzhiyun #define LCD_INVMASK(x) ((x) & 0x3F00000)
55*4882a593Smuzhiyun /* LCD Raster Ctrl Register */
56*4882a593Smuzhiyun #define LCD_TFT_24BPP_MODE (1 << 25)
57*4882a593Smuzhiyun #define LCD_TFT_24BPP_UNPACK (1 << 26)
58*4882a593Smuzhiyun #define LCD_PALMODE_RAWDATA (0x02 << 20)
59*4882a593Smuzhiyun #define LCD_TFT_MODE (0x01 << 7)
60*4882a593Smuzhiyun #define LCD_RASTER_ENABLE (0x01 << 0)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Macro definitions */
64*4882a593Smuzhiyun #define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3)
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun struct am335x_lcdhw {
67*4882a593Smuzhiyun unsigned int pid; /* 0x00 */
68*4882a593Smuzhiyun unsigned int ctrl; /* 0x04 */
69*4882a593Smuzhiyun unsigned int gap0; /* 0x08 */
70*4882a593Smuzhiyun unsigned int lidd_ctrl; /* 0x0C */
71*4882a593Smuzhiyun unsigned int lidd_cs0_conf; /* 0x10 */
72*4882a593Smuzhiyun unsigned int lidd_cs0_addr; /* 0x14 */
73*4882a593Smuzhiyun unsigned int lidd_cs0_data; /* 0x18 */
74*4882a593Smuzhiyun unsigned int lidd_cs1_conf; /* 0x1C */
75*4882a593Smuzhiyun unsigned int lidd_cs1_addr; /* 0x20 */
76*4882a593Smuzhiyun unsigned int lidd_cs1_data; /* 0x24 */
77*4882a593Smuzhiyun unsigned int raster_ctrl; /* 0x28 */
78*4882a593Smuzhiyun unsigned int raster_timing0; /* 0x2C */
79*4882a593Smuzhiyun unsigned int raster_timing1; /* 0x30 */
80*4882a593Smuzhiyun unsigned int raster_timing2; /* 0x34 */
81*4882a593Smuzhiyun unsigned int raster_subpanel; /* 0x38 */
82*4882a593Smuzhiyun unsigned int raster_subpanel2; /* 0x3C */
83*4882a593Smuzhiyun unsigned int lcddma_ctrl; /* 0x40 */
84*4882a593Smuzhiyun unsigned int lcddma_fb0_base; /* 0x44 */
85*4882a593Smuzhiyun unsigned int lcddma_fb0_ceiling; /* 0x48 */
86*4882a593Smuzhiyun unsigned int lcddma_fb1_base; /* 0x4C */
87*4882a593Smuzhiyun unsigned int lcddma_fb1_ceiling; /* 0x50 */
88*4882a593Smuzhiyun unsigned int sysconfig; /* 0x54 */
89*4882a593Smuzhiyun unsigned int irqstatus_raw; /* 0x58 */
90*4882a593Smuzhiyun unsigned int irqstatus; /* 0x5C */
91*4882a593Smuzhiyun unsigned int irqenable_set; /* 0x60 */
92*4882a593Smuzhiyun unsigned int irqenable_clear; /* 0x64 */
93*4882a593Smuzhiyun unsigned int gap1; /* 0x68 */
94*4882a593Smuzhiyun unsigned int clkc_enable; /* 0x6C */
95*4882a593Smuzhiyun unsigned int clkc_reset; /* 0x70 */
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
99*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
100*4882a593Smuzhiyun
lcd_get_size(int * line_length)101*4882a593Smuzhiyun int lcd_get_size(int *line_length)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
104*4882a593Smuzhiyun return *line_length * panel_info.vl_row + 0x20;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
am335xfb_init(struct am335x_lcdpanel * panel)107*4882a593Smuzhiyun int am335xfb_init(struct am335x_lcdpanel *panel)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun u32 raster_ctrl = 0;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun if (0 == gd->fb_base) {
112*4882a593Smuzhiyun printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
113*4882a593Smuzhiyun return -1;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun if (0 == panel) {
116*4882a593Smuzhiyun printf("ERROR: missing ptr to am335x_lcdpanel!\n");
117*4882a593Smuzhiyun return -1;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* We can already set the bits for the raster_ctrl in this check */
121*4882a593Smuzhiyun switch (panel->bpp) {
122*4882a593Smuzhiyun case 16:
123*4882a593Smuzhiyun break;
124*4882a593Smuzhiyun case 32:
125*4882a593Smuzhiyun raster_ctrl |= LCD_TFT_24BPP_UNPACK;
126*4882a593Smuzhiyun /* fallthrough */
127*4882a593Smuzhiyun case 24:
128*4882a593Smuzhiyun raster_ctrl |= LCD_TFT_24BPP_MODE;
129*4882a593Smuzhiyun break;
130*4882a593Smuzhiyun default:
131*4882a593Smuzhiyun pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
132*4882a593Smuzhiyun return -1;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
136*4882a593Smuzhiyun panel->hactive, panel->vactive, panel->bpp,
137*4882a593Smuzhiyun panel->hfp, panel->hbp, panel->hsw);
138*4882a593Smuzhiyun debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n",
139*4882a593Smuzhiyun panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div);
140*4882a593Smuzhiyun debug("using frambuffer at 0x%08x with size %d.\n",
141*4882a593Smuzhiyun (unsigned int)gd->fb_base, FBSIZE(panel));
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* palette default entry */
144*4882a593Smuzhiyun memset((void *)gd->fb_base, 0, 0x20);
145*4882a593Smuzhiyun *(unsigned int *)gd->fb_base = 0x4000;
146*4882a593Smuzhiyun /* point fb behind palette */
147*4882a593Smuzhiyun gd->fb_base += 0x20;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* turn ON display through powercontrol function if accessible */
150*4882a593Smuzhiyun if (0 != panel->panel_power_ctrl)
151*4882a593Smuzhiyun panel->panel_power_ctrl(1);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun debug("am335x-fb: wait for stable power ...\n");
154*4882a593Smuzhiyun mdelay(panel->pup_delay);
155*4882a593Smuzhiyun lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
156*4882a593Smuzhiyun lcdhw->raster_ctrl = 0;
157*4882a593Smuzhiyun lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
158*4882a593Smuzhiyun lcdhw->lcddma_fb0_base = gd->fb_base;
159*4882a593Smuzhiyun lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
160*4882a593Smuzhiyun lcdhw->lcddma_fb1_base = gd->fb_base;
161*4882a593Smuzhiyun lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
162*4882a593Smuzhiyun lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
165*4882a593Smuzhiyun LCD_HORMSB(panel->hactive) |
166*4882a593Smuzhiyun LCD_HFPLSB(panel->hfp) |
167*4882a593Smuzhiyun LCD_HBPLSB(panel->hbp) |
168*4882a593Smuzhiyun LCD_HSWLSB(panel->hsw);
169*4882a593Smuzhiyun lcdhw->raster_timing1 = LCD_VBP(panel->vbp) |
170*4882a593Smuzhiyun LCD_VFP(panel->vfp) |
171*4882a593Smuzhiyun LCD_VSW(panel->vsw) |
172*4882a593Smuzhiyun LCD_VERLSB(panel->vactive);
173*4882a593Smuzhiyun lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) |
174*4882a593Smuzhiyun LCD_VERMSB(panel->vactive) |
175*4882a593Smuzhiyun LCD_INVMASK(panel->pol) |
176*4882a593Smuzhiyun LCD_HBPMSB(panel->hbp) |
177*4882a593Smuzhiyun LCD_HFPMSB(panel->hfp) |
178*4882a593Smuzhiyun 0x0000FF00; /* clk cycles for ac-bias */
179*4882a593Smuzhiyun lcdhw->raster_ctrl = raster_ctrl |
180*4882a593Smuzhiyun LCD_PALMODE_RAWDATA |
181*4882a593Smuzhiyun LCD_TFT_MODE |
182*4882a593Smuzhiyun LCD_RASTER_ENABLE;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun debug("am335x-fb: waiting picture to be stable.\n.");
185*4882a593Smuzhiyun mdelay(panel->pon_delay);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return 0;
188*4882a593Smuzhiyun }
189