1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * MUSB OTG driver DMA controller abstraction
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright 2005 Mentor Graphics Corporation
5*4882a593Smuzhiyun * Copyright (C) 2005-2006 by Texas Instruments
6*4882a593Smuzhiyun * Copyright (C) 2006-2007 Nokia Corporation
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef __MUSB_DMA_H__
12*4882a593Smuzhiyun #define __MUSB_DMA_H__
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun struct musb_hw_ep;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * DMA Controller Abstraction
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * DMA Controllers are abstracted to allow use of a variety of different
20*4882a593Smuzhiyun * implementations of DMA, as allowed by the Inventra USB cores. On the
21*4882a593Smuzhiyun * host side, usbcore sets up the DMA mappings and flushes caches; on the
22*4882a593Smuzhiyun * peripheral side, the gadget controller driver does. Responsibilities
23*4882a593Smuzhiyun * of a DMA controller driver include:
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * - Handling the details of moving multiple USB packets
26*4882a593Smuzhiyun * in cooperation with the Inventra USB core, including especially
27*4882a593Smuzhiyun * the correct RX side treatment of short packets and buffer-full
28*4882a593Smuzhiyun * states (both of which terminate transfers).
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * - Knowing the correlation between dma channels and the
31*4882a593Smuzhiyun * Inventra core's local endpoint resources and data direction.
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * - Maintaining a list of allocated/available channels.
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun * - Updating channel status on interrupts,
36*4882a593Smuzhiyun * whether shared with the Inventra core or separate.
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define DMA_ADDR_INVALID (~(dma_addr_t)0)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #ifndef CONFIG_USB_MUSB_PIO_ONLY
42*4882a593Smuzhiyun #define is_dma_capable() (1)
43*4882a593Smuzhiyun #else
44*4882a593Smuzhiyun #define is_dma_capable() (0)
45*4882a593Smuzhiyun #endif
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #ifdef CONFIG_USB_TI_CPPI_DMA
48*4882a593Smuzhiyun #define is_cppi_enabled() 1
49*4882a593Smuzhiyun #else
50*4882a593Smuzhiyun #define is_cppi_enabled() 0
51*4882a593Smuzhiyun #endif
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #ifdef CONFIG_USB_TUSB_OMAP_DMA
54*4882a593Smuzhiyun #define tusb_dma_omap() 1
55*4882a593Smuzhiyun #else
56*4882a593Smuzhiyun #define tusb_dma_omap() 0
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * DMA channel status ... updated by the dma controller driver whenever that
61*4882a593Smuzhiyun * status changes, and protected by the overall controller spinlock.
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun enum dma_channel_status {
64*4882a593Smuzhiyun /* unallocated */
65*4882a593Smuzhiyun MUSB_DMA_STATUS_UNKNOWN,
66*4882a593Smuzhiyun /* allocated ... but not busy, no errors */
67*4882a593Smuzhiyun MUSB_DMA_STATUS_FREE,
68*4882a593Smuzhiyun /* busy ... transactions are active */
69*4882a593Smuzhiyun MUSB_DMA_STATUS_BUSY,
70*4882a593Smuzhiyun /* transaction(s) aborted due to ... dma or memory bus error */
71*4882a593Smuzhiyun MUSB_DMA_STATUS_BUS_ABORT,
72*4882a593Smuzhiyun /* transaction(s) aborted due to ... core error or USB fault */
73*4882a593Smuzhiyun MUSB_DMA_STATUS_CORE_ABORT
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct dma_controller;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /**
79*4882a593Smuzhiyun * struct dma_channel - A DMA channel.
80*4882a593Smuzhiyun * @private_data: channel-private data
81*4882a593Smuzhiyun * @max_len: the maximum number of bytes the channel can move in one
82*4882a593Smuzhiyun * transaction (typically representing many USB maximum-sized packets)
83*4882a593Smuzhiyun * @actual_len: how many bytes have been transferred
84*4882a593Smuzhiyun * @status: current channel status (updated e.g. on interrupt)
85*4882a593Smuzhiyun * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
86*4882a593Smuzhiyun *
87*4882a593Smuzhiyun * channels are associated with an endpoint for the duration of at least
88*4882a593Smuzhiyun * one usb transfer.
89*4882a593Smuzhiyun */
90*4882a593Smuzhiyun struct dma_channel {
91*4882a593Smuzhiyun void *private_data;
92*4882a593Smuzhiyun /* FIXME not void* private_data, but a dma_controller * */
93*4882a593Smuzhiyun size_t max_len;
94*4882a593Smuzhiyun size_t actual_len;
95*4882a593Smuzhiyun enum dma_channel_status status;
96*4882a593Smuzhiyun bool desired_mode;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun * dma_channel_status - return status of dma channel
101*4882a593Smuzhiyun * @c: the channel
102*4882a593Smuzhiyun *
103*4882a593Smuzhiyun * Returns the software's view of the channel status. If that status is BUSY
104*4882a593Smuzhiyun * then it's possible that the hardware has completed (or aborted) a transfer,
105*4882a593Smuzhiyun * so the driver needs to update that status.
106*4882a593Smuzhiyun */
107*4882a593Smuzhiyun static inline enum dma_channel_status
dma_channel_status(struct dma_channel * c)108*4882a593Smuzhiyun dma_channel_status(struct dma_channel *c)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /**
114*4882a593Smuzhiyun * struct dma_controller - A DMA Controller.
115*4882a593Smuzhiyun * @start: call this to start a DMA controller;
116*4882a593Smuzhiyun * return 0 on success, else negative errno
117*4882a593Smuzhiyun * @stop: call this to stop a DMA controller
118*4882a593Smuzhiyun * return 0 on success, else negative errno
119*4882a593Smuzhiyun * @channel_alloc: call this to allocate a DMA channel
120*4882a593Smuzhiyun * @channel_release: call this to release a DMA channel
121*4882a593Smuzhiyun * @channel_abort: call this to abort a pending DMA transaction,
122*4882a593Smuzhiyun * returning it to FREE (but allocated) state
123*4882a593Smuzhiyun *
124*4882a593Smuzhiyun * Controllers manage dma channels.
125*4882a593Smuzhiyun */
126*4882a593Smuzhiyun struct dma_controller {
127*4882a593Smuzhiyun int (*start)(struct dma_controller *);
128*4882a593Smuzhiyun int (*stop)(struct dma_controller *);
129*4882a593Smuzhiyun struct dma_channel *(*channel_alloc)(struct dma_controller *,
130*4882a593Smuzhiyun struct musb_hw_ep *, u8 is_tx);
131*4882a593Smuzhiyun void (*channel_release)(struct dma_channel *);
132*4882a593Smuzhiyun int (*channel_program)(struct dma_channel *channel,
133*4882a593Smuzhiyun u16 maxpacket, u8 mode,
134*4882a593Smuzhiyun dma_addr_t dma_addr,
135*4882a593Smuzhiyun u32 length);
136*4882a593Smuzhiyun int (*channel_abort)(struct dma_channel *);
137*4882a593Smuzhiyun int (*is_compatible)(struct dma_channel *channel,
138*4882a593Smuzhiyun u16 maxpacket,
139*4882a593Smuzhiyun void *buf, u32 length);
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* called after channel_program(), may indicate a fault */
143*4882a593Smuzhiyun extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun extern struct dma_controller *__init
147*4882a593Smuzhiyun dma_controller_create(struct musb *, void __iomem *);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun extern void dma_controller_destroy(struct dma_controller *);
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #endif /* __MUSB_DMA_H__ */
152