1 /*
2 * USB 3.0 DRD Controller
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <watchdog.h>
12 #include <usb.h>
13 #include <asm/arch/psc_defs.h>
14 #include <asm/io.h>
15 #include <linux/usb/dwc3.h>
16 #include <asm/arch/xhci-keystone.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include "xhci.h"
20
21 struct kdwc3_irq_regs {
22 u32 revision; /* 0x000 */
23 u32 rsvd0[3];
24 u32 sysconfig; /* 0x010 */
25 u32 rsvd1[1];
26 u32 irq_eoi;
27 u32 rsvd2[1];
28 struct {
29 u32 raw_status;
30 u32 status;
31 u32 enable_set;
32 u32 enable_clr;
33 } irqs[16];
34 };
35
36 struct keystone_xhci {
37 struct xhci_hccr *hcd;
38 struct dwc3 *dwc3_reg;
39 struct xhci_hcor *hcor;
40 struct kdwc3_irq_regs *usbss;
41 struct keystone_xhci_phy *phy;
42 };
43
44 struct keystone_xhci keystone;
45
keystone_xhci_phy_set(struct keystone_xhci_phy * phy)46 static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy)
47 {
48 u32 val;
49
50 /*
51 * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
52 * It should always be cleared because our USB PHY has an onchip VBUS
53 * analog comparator.
54 */
55 val = readl(&phy->phy_clock);
56 /* quit selecting the vbusvldextsel by default! */
57 val &= ~USB3_PHY_OTG_VBUSVLDECTSEL;
58 writel(val, &phy->phy_clock);
59 }
60
keystone_xhci_phy_unset(struct keystone_xhci_phy * phy)61 static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
62 {
63 u32 val;
64
65 /* Disable the PHY REFCLK clock gate */
66 val = readl(&phy->phy_clock);
67 val &= ~USB3_PHY_REF_SSP_EN;
68 writel(val, &phy->phy_clock);
69 }
70
keystone_xhci_core_init(struct dwc3 * dwc3_reg)71 static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
72 {
73 int ret;
74
75 ret = dwc3_core_init(dwc3_reg);
76 if (ret) {
77 debug("failed to initialize core\n");
78 return -EINVAL;
79 }
80
81 /* We are hard-coding DWC3 core to Host Mode */
82 dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
83
84 return 0;
85 }
86
xhci_hcd_init(int index,struct xhci_hccr ** ret_hccr,struct xhci_hcor ** ret_hcor)87 int xhci_hcd_init(int index,
88 struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor)
89 {
90 u32 val;
91 int ret;
92 struct xhci_hccr *hcd;
93 struct xhci_hcor *hcor;
94 struct kdwc3_irq_regs *usbss;
95 struct keystone_xhci_phy *phy;
96
97 usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE;
98 phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE;
99
100 /* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */
101 val = readl(&(phy->phy_clock));
102 val |= USB3_PHY_REF_SSP_EN;
103 writel(val, &phy->phy_clock);
104
105 mdelay(100);
106
107 /* Release USB from reset */
108 ret = psc_enable_module(KS2_LPSC_USB);
109 if (ret) {
110 puts("Cannot enable USB module");
111 return -1;
112 }
113
114 mdelay(100);
115
116 /* Initialize usb phy */
117 keystone_xhci_phy_set(phy);
118
119 /* soft reset usbss */
120 writel(1, &usbss->sysconfig);
121 while (readl(&usbss->sysconfig) & 1)
122 ;
123
124 val = readl(&usbss->revision);
125 debug("usbss revision %x\n", val);
126
127 /* Initialize usb core */
128 hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE;
129 keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE +
130 DWC3_REG_OFFSET);
131
132 keystone_xhci_core_init(keystone.dwc3_reg);
133
134 /* set register addresses */
135 hcor = (struct xhci_hcor *)((uint32_t)hcd +
136 HC_LENGTH(readl(&hcd->cr_capbase)));
137
138 debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n",
139 (u32)hcd, (u32)hcor,
140 (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase)));
141
142 keystone.usbss = usbss;
143 keystone.phy = phy;
144 keystone.hcd = hcd;
145 keystone.hcor = hcor;
146
147 *ret_hccr = hcd;
148 *ret_hcor = hcor;
149
150 return 0;
151 }
152
keystone_xhci_phy_suspend(void)153 static int keystone_xhci_phy_suspend(void)
154 {
155 int loop_cnt = 0;
156 struct xhci_hcor *hcor;
157 uint32_t *portsc_1 = NULL;
158 uint32_t *portsc_2 = NULL;
159 u32 val, usb2_pls, usb3_pls, event_q;
160 struct dwc3 *dwc3_reg = keystone.dwc3_reg;
161
162 /* set register addresses */
163 hcor = keystone.hcor;
164
165 /* Bypass Scrambling and Set Shorter Training sequence for simulation */
166 val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2);
167 writel(val, &dwc3_reg->g_ctl);
168
169 /* GUSB2PHYCFG */
170 val = readl(&dwc3_reg->g_usb2phycfg[0]);
171
172 /* assert bit 6 (SusPhy) */
173 val |= DWC3_GUSB2PHYCFG_SUSPHY;
174 writel(val, &dwc3_reg->g_usb2phycfg[0]);
175
176 /* GUSB3PIPECTL */
177 val = readl(&dwc3_reg->g_usb3pipectl[0]);
178
179 /*
180 * assert bit 29 to allow PHY to go to suspend when idle
181 * and cause the USB3 SS PHY to enter suspend mode
182 */
183 val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY);
184 writel(val, &dwc3_reg->g_usb3pipectl[0]);
185
186 /*
187 * Steps necessary to allow controller to suspend even when
188 * VBUS is HIGH:
189 * - Init DCFG[2:0] (DevSpd) to: 1=FS
190 * - Init GEVNTADR0 to point to an eventQ
191 * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ
192 * - Init DCTL::Run_nStop = 1
193 */
194 writel(0x00020001, &dwc3_reg->d_cfg);
195 /* TODO: local2global( (Uint32) eventQ )? */
196 writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo);
197 writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi);
198 writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz);
199 /* Run */
200 writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl);
201
202 mdelay(100);
203
204 /* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */
205 portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc);
206 portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc);
207 usb2_pls = 0;
208 usb3_pls = 0;
209 do {
210 ++loop_cnt;
211 usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5;
212 usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5;
213 } while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000);
214
215 if (usb2_pls != 0x4 || usb3_pls != 0x4) {
216 debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n",
217 usb2_pls, usb3_pls);
218 return -1;
219 }
220
221 debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt);
222 return 0;
223 }
224
xhci_hcd_stop(int index)225 void xhci_hcd_stop(int index)
226 {
227 /* Disable USB */
228 if (keystone_xhci_phy_suspend())
229 return;
230
231 if (psc_disable_module(KS2_LPSC_USB)) {
232 debug("PSC disable module USB failed!\n");
233 return;
234 }
235
236 /* Disable PHY */
237 keystone_xhci_phy_unset(keystone.phy);
238
239 /* memset(&keystone, 0, sizeof(struct keystone_xhci)); */
240 debug("xhci_hcd_stop OK.\n");
241 }
242