1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2012
3*4882a593Smuzhiyun * eInfochips Ltd. <www.einfochips.com>
4*4882a593Smuzhiyun * Written-by: Ajay Bhargav <contact@8051projects.net>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * (C) Copyright 2009
7*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <common.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <usb.h>
15*4882a593Smuzhiyun #include <asm/arch/cpu.h>
16*4882a593Smuzhiyun #include <asm/arch/armada100.h>
17*4882a593Smuzhiyun #include <asm/arch/utmi-armada100.h>
18*4882a593Smuzhiyun
utmi_phy_init(void)19*4882a593Smuzhiyun static int utmi_phy_init(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct armd1usb_phy_reg *phy_regs =
22*4882a593Smuzhiyun (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
23*4882a593Smuzhiyun int timeout;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
26*4882a593Smuzhiyun udelay(1000);
27*4882a593Smuzhiyun setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
30*4882a593Smuzhiyun setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Calibrate pll */
35*4882a593Smuzhiyun timeout = 10000;
36*4882a593Smuzhiyun while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
37*4882a593Smuzhiyun ;
38*4882a593Smuzhiyun if (!timeout)
39*4882a593Smuzhiyun return -1;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun udelay(200);
42*4882a593Smuzhiyun setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
43*4882a593Smuzhiyun udelay(400);
44*4882a593Smuzhiyun clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun udelay(200);
47*4882a593Smuzhiyun setbits_le32(&phy_regs->utmi_tx, RCAL_START);
48*4882a593Smuzhiyun udelay(400);
49*4882a593Smuzhiyun clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun timeout = 10000;
52*4882a593Smuzhiyun while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
53*4882a593Smuzhiyun ;
54*4882a593Smuzhiyun if (!timeout)
55*4882a593Smuzhiyun return -1;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * Initialize USB host controller's UTMI Physical interface
62*4882a593Smuzhiyun */
utmi_init(void)63*4882a593Smuzhiyun int utmi_init(void)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct armd1mpmu_registers *mpmu_regs =
66*4882a593Smuzhiyun (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun struct armd1apmu_registers *apmu_regs =
69*4882a593Smuzhiyun (struct armd1apmu_registers *)ARMD1_APMU_BASE;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Turn on 26Mhz ref clock for UTMI PLL */
72*4882a593Smuzhiyun setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* USB Clock reset */
75*4882a593Smuzhiyun writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
76*4882a593Smuzhiyun writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* Initialize UTMI transceiver */
79*4882a593Smuzhiyun return utmi_phy_init();
80*4882a593Smuzhiyun }
81